forked from Github_Repos/cvw
198 lines
9.3 KiB
Systemverilog
198 lines
9.3 KiB
Systemverilog
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///////////////////////////////////////////
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// lsu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Load/Store Unit
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// Top level of the memory-stage hart logic
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// Contains data cache, DTLB, subword read/write datapath, interface to external bus
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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// *** Ross Thompson amo misalignment check?
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module lsu (
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input logic clk, reset,
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input logic StallM, FlushM, StallW, FlushW,
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//output logic DataStall,
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// Memory Stage
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input logic [1:0] MemRWM,
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input logic [`XLEN-1:0] MemAdrM,
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input logic [2:0] Funct3M,
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//input logic [`XLEN-1:0] ReadDataW,
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input logic [`XLEN-1:0] WriteDataM,
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input logic [1:0] AtomicM,
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input logic CommitM,
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output logic [`PA_BITS-1:0] MemPAdrM,
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output logic MemReadM, MemWriteM,
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output logic [1:0] AtomicMaskedM,
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output logic DataMisalignedM,
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output logic CommittedM,
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// Writeback Stage
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input logic MemAckW,
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input logic [`XLEN-1:0] ReadDataW,
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output logic SquashSCW,
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// faults
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input logic NonBusTrapM,
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input logic DataAccessFaultM,
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output logic DTLBLoadPageFaultM, DTLBStorePageFaultM,
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output logic LoadMisalignedFaultM, LoadAccessFaultM,
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output logic StoreMisalignedFaultM, StoreAccessFaultM,
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// mmu management
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] PageTableEntryM,
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input logic [1:0] PageTypeM,
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM,
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input logic DTLBWriteM, DTLBFlushM,
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output logic DTLBMissM, DTLBHitM,
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// PMA/PMP (inside mmu) signals
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input logic [31:0] HADDR, // *** replace all of these H inputs with physical adress once pma checkers have been edited to use paddr as well.
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input logic [2:0] HSIZE, HBURST,
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input logic HWRITE,
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input logic AtomicAccessM, WriteAccessM, ReadAccessM, // execute access is hardwired to zero in this mmu because we're only working with data in the M stage.
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input logic [63:0] PMPCFG01_REGW, PMPCFG23_REGW, // *** all of these come from the privileged unit, so thwyre gonna have to come over into ifu and dmem
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0], // *** this one especially has a large note attached to it in pmpchecker.
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output logic PMALoadAccessFaultM, PMAStoreAccessFaultM,
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output logic PMPLoadAccessFaultM, PMPStoreAccessFaultM, // *** can these be parameterized? we dont need the m stage ones for the immu and vice versa.
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output logic DSquashBusAccessM,
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output logic [5:0] DHSELRegionsM
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);
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logic SquashSCM;
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logic DTLBPageFaultM;
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logic MemAccessM;
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logic [1:0] CurrState, NextState;
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logic preCommittedM;
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localparam STATE_READY = 0;
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localparam STATE_FETCH = 1;
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localparam STATE_FETCH_AMO = 2;
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localparam STATE_STALLED = 3;
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logic PMPInstrAccessFaultF, PMAInstrAccessFaultF; // *** these are just so that the mmu has somewhere to put these outputs since they aren't used in dmem
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// *** if you're allowed to parameterize outputs/ inputs existence, these are an easy delete.
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mmu #(.ENTRY_BITS(`DTLB_ENTRY_BITS), .IMMU(0)) dmmu(.TLBAccessType(MemRWM), .VirtualAddress(MemAdrM), .Size(Funct3M[1:0]),
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.PTEWriteVal(PageTableEntryM), .PageTypeWriteVal(PageTypeM),
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.TLBWrite(DTLBWriteM), .TLBFlush(DTLBFlushM),
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.PhysicalAddress(MemPAdrM), .TLBMiss(DTLBMissM),
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.TLBHit(DTLBHitM), .TLBPageFault(DTLBPageFaultM),
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.ExecuteAccessF(1'b0),
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.SquashBusAccess(DSquashBusAccessM), .HSELRegions(DHSELRegionsM),
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.*); // *** the pma/pmp instruction acess faults don't really matter here. is it possible to parameterize which outputs exist?
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// Specify which type of page fault is occurring
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assign DTLBLoadPageFaultM = DTLBPageFaultM & MemRWM[1];
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assign DTLBStorePageFaultM = DTLBPageFaultM & MemRWM[0];
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// Determine if an Unaligned access is taking place
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always_comb
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case(Funct3M[1:0])
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2'b00: DataMisalignedM = 0; // lb, sb, lbu
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2'b01: DataMisalignedM = MemAdrM[0]; // lh, sh, lhu
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2'b10: DataMisalignedM = MemAdrM[1] | MemAdrM[0]; // lw, sw, flw, fsw, lwu
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2'b11: DataMisalignedM = |MemAdrM[2:0]; // ld, sd, fld, fsd
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endcase
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// Squash unaligned data accesses and failed store conditionals
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// *** this is also the place to squash if the cache is hit
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// Changed DataMisalignedM to a larger combination of trap sources
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// NonBusTrapM is anything that the bus doesn't contribute to producing
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// By contrast, using TrapM results in circular logic errors
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assign MemReadM = MemRWM[1] & ~NonBusTrapM & CurrState != STATE_STALLED;
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assign MemWriteM = MemRWM[0] & ~NonBusTrapM && ~SquashSCM & CurrState != STATE_STALLED;
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assign AtomicMaskedM = CurrState != STATE_STALLED ? AtomicM : 2'b00 ;
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assign MemAccessM = |MemRWM;
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// Determine if M stage committed
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// Reset whenever unstalled. Set when access successfully occurs
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flopr #(1) committedMreg(clk,reset,(CommittedM | CommitM) & StallM,preCommittedM);
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assign CommittedM = preCommittedM | CommitM;
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// Determine if address is valid
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assign LoadMisalignedFaultM = DataMisalignedM & MemRWM[1];
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assign LoadAccessFaultM = DataAccessFaultM & MemRWM[1];
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assign StoreMisalignedFaultM = DataMisalignedM & MemRWM[0];
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assign StoreAccessFaultM = DataAccessFaultM & MemRWM[0];
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// Handle atomic load reserved / store conditional
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generate
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if (`A_SUPPORTED) begin // atomic instructions supported
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logic [`PA_BITS-1:2] ReservationPAdrW;
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logic ReservationValidM, ReservationValidW;
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logic lrM, scM, WriteAdrMatchM;
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assign lrM = MemReadM && AtomicM[0];
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assign scM = MemRWM[0] && AtomicM[0];
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assign WriteAdrMatchM = MemRWM[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
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assign SquashSCM = scM && ~WriteAdrMatchM;
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always_comb begin // ReservationValidM (next value of valid reservation)
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if (lrM) ReservationValidM = 1; // set valid on load reserve
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else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
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else ReservationValidM = ReservationValidW; // otherwise don't change valid
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end
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flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
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flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
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flopenrc #(1) squashreg(clk, reset, FlushW, ~StallW, SquashSCM, SquashSCW);
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end else begin // Atomic operations not supported
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assign SquashSCM = 0;
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assign SquashSCW = 0;
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end
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endgenerate
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// Data stall
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//assign DataStall = 0;
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// Ross Thompson April 22, 2021
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// for now we need to handle the issue where the data memory interface repeately
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// requests data from memory rather than issuing a single request.
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flopr #(2) stateReg(.clk(clk),
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.reset(reset),
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.d(NextState),
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.q(CurrState));
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always_comb begin
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case (CurrState)
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STATE_READY: if (MemRWM[1] & MemRWM[0]) NextState = STATE_FETCH_AMO; // *** should be some misalign check
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else if (MemAccessM & ~DataMisalignedM) NextState = STATE_FETCH;
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else NextState = STATE_READY;
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STATE_FETCH_AMO: if (MemAckW) NextState = STATE_FETCH;
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else NextState = STATE_FETCH_AMO;
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STATE_FETCH: if (MemAckW & ~StallW) NextState = STATE_READY;
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else if (MemAckW & StallW) NextState = STATE_STALLED;
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else NextState = STATE_FETCH;
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STATE_STALLED: if (~StallW) NextState = STATE_READY;
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else NextState = STATE_STALLED;
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default: NextState = STATE_READY;
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endcase // case (CurrState)
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end
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endmodule
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