forked from Github_Repos/cvw
12 lines
278 B
Perl
12 lines
278 B
Perl
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#!/usr/bin/perl -w
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# vclean.pl
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# David_Harris@hmc.edu 7 December 2023
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# Identifies unused signals in Verilog files
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# verilator should do this, but it also reports partially used signals
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for (my $i=0; $i<=$#ARGV; $i++) {
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my $fname = $ARGV[$i];
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printf ("$fname\n");
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}
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