forked from Github_Repos/cvw
53 lines
2.1 KiB
Systemverilog
53 lines
2.1 KiB
Systemverilog
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///////////////////////////////////////////
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// regfile.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: 3-port register file
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-macros.sv"
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module regfile #(parameter XLEN=32) (
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input logic clk, reset,
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input logic we3,
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input logic [ 4:0] a1, a2, a3,
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input logic [XLEN-1:0] wd3,
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output logic [XLEN-1:0] rd1, rd2);
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logic [XLEN-1:0] rf[31:0];
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integer i;
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// three ported register file
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// read two ports combinationally (A1/RD1, A2/RD2)
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// write third port on rising edge of clock (A3/WD3/WE3)
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// write occurs on falling edge of clock
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// register 0 hardwired to 0
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// reset is intended for simulation only, not synthesis
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always_ff @(negedge clk or posedge reset)
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if (reset) for(i=0; i<32; i++) rf[i] <= 0;
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else if (we3) rf[a3] <= wd3;
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assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
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assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;
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endmodule
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