forked from Github_Repos/cvw
29 lines
1.1 KiB
Markdown
29 lines
1.1 KiB
Markdown
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# CORE-V Wally Test Plan
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CORE-V Wally is tested in the following ways:
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* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model.
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* Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV.
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* ***pending: Run random tests generated by risc-dv
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* Run CoreMark and Embench benchmarks.
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* Run performance validation against reference models for the branch predictor and caches.
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* Run the TestFloat suite against all precisions of all operations for the FPU unit.
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* *** 83.5% coverage of statements, branches, expressions, and FSM states and transitions
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* Boot Buildroot Linux in lock-step against ImperasDV.
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* Boot Buildroot Linux on an FPGA and run programs.
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# Running Tests
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#
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# Detailed Test Plans
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The test plans for specific units are lined below:
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* Privileged Unit
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* Memory Management Unit
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* Peripherals
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* Branch Predictor Performance Validation
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* Cache Performance Validation
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Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris.
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