forked from Github_Repos/cvw
89 lines
2.4 KiB
Systemverilog
89 lines
2.4 KiB
Systemverilog
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module mult_cs #(parameter WIDTH = 8)
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(a, b, tc, sum, carry);
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input logic [WIDTH-1:0] a;
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input logic [WIDTH-1:0] b;
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input logic tc;
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output logic [2*WIDTH-1:0] sum, carry;
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// PP array
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logic [2*WIDTH-1:0] pp_array [0:WIDTH-1];
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logic [2*WIDTH-1:0] tmp_sum, tmp_carry;
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logic [2*WIDTH-1:0] a_padded;
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logic [2*WIDTH-1:0] b_padded;
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logic [2*WIDTH-1:0] product;
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assign a_padded = a;
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assign b_padded = b;
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always_comb
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begin
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logic [2*WIDTH-1:0] temp_pp_array [0 : WIDTH-1];
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logic [2*WIDTH-1:0] next_pp_array [0 : WIDTH-1];
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logic [2*WIDTH-1:0] temp_pp;
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logic [2*WIDTH-1:0] tmp_pp_carry;
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logic [WIDTH+2:0] temp_b_padded;
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logic temp_bitgroup;
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integer bit_pair, pp_count, i;
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temp_pp_array[0] = {2*WIDTH{1'b0}};
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// For each multiplicand
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for (bit_pair=0; bit_pair < WIDTH; bit_pair=bit_pair+1)
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begin
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// Shift to the right multiplier
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temp_b_padded = (b_padded >> (bit_pair));
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temp_bitgroup = temp_b_padded[0];
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// PP generation
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case (temp_bitgroup)
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1'b0 :
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temp_pp = {2*WIDTH{1'b0}};
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1'b1 :
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temp_pp = a_padded;
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default : temp_pp = {2*WIDTH{1'b0}};
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endcase
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// Shift to the left via P&H
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temp_pp = temp_pp << (bit_pair);
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temp_pp_array[bit_pair] = temp_pp;
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end
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pp_count = WIDTH;
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// Wallace Tree (I do not think this is really a Wallace tree (misses HA))
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while (pp_count > 2)
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begin
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for (i=0 ; i < (pp_count/3) ; i = i+1)
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begin
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next_pp_array[i*2] = temp_pp_array[i*3]^temp_pp_array[i*3+1]^temp_pp_array[i*3+2];
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tmp_pp_carry = (temp_pp_array[i*3] & temp_pp_array[i*3+1]) |
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(temp_pp_array[i*3+1] & temp_pp_array[i*3+2]) |
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(temp_pp_array[i*3] & temp_pp_array[i*3+2]);
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next_pp_array[i*2+1] = tmp_pp_carry << 1;
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end
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if ((pp_count % 3) > 0)
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begin
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for (i=0 ; i < (pp_count % 3) ; i=i+1)
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next_pp_array[2 * (pp_count/3) + i] = temp_pp_array[3 * (pp_count/3) + i];
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end
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for (i=0 ; i < WIDTH ; i=i+1)
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temp_pp_array[i] = next_pp_array[i];
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pp_count = pp_count - (pp_count/3);
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end
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tmp_sum = temp_pp_array[0];
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if (pp_count > 1)
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tmp_carry = temp_pp_array[1];
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else
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tmp_carry = {2*WIDTH{1'b0}};
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end
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assign sum = tmp_sum;
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assign carry = tmp_carry;
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endmodule // mult_cs
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