cvw/fpga/generator/probe

#!/usr/bin/python3
###########################################
## fpgaTop.sv
##
## Written: jacob.pease@okstate.edu 06 April 2023
## Modified: 
##
## Purpose: Generates 1 entry in a ILA debugger
## 
## A component of the Wally configurable RISC-V project.
## 
## Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
##
## Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
## files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, 
## modify, merge, publish, distribute, sublicense, and#or sell copies of the Software, and to permit persons to whom the Software 
## is furnished to do so, subject to the following conditions:
##
## The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
##
## THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 
## OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 
## BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT 
## OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
###########################################

import sys

def usage():
	print("Usage: ./probes name width probenum")

def header():
	return """create_debug_core u_ila_0 ila

set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
startgroup 
set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
endgroup
connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]"""

def convertLine(x):
	temp = x.split()
	temp[1] = int(temp[1])
	return tuple(temp)

def probeBits( probe ):
	str = ''

	if (probe[1] > 1):
		for i in range(probe[1]):
			if i != (probe[1]-1):
				str = str + f"{{{probe[0]}[{i}]}} "
			else:
				str = str + f"{{{probe[0]}[{i}]}} "

	else:
		str = f'{{{probe[0]}}}'

	return str

def printProbe( probe, i ):
	bits = probeBits(probe)

	return (
	    f'create_debug_port u_ila_0 probe\n'
	    f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{i}]\n'
	    f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{i}]\n'
	    f'connect_debug_port u_ila_0/probe{i} [get_nets [list {bits}]]\n\n'
	)

def main(args):
	if (len(args) != 3):
		usage()

	name = args[0]
	width = int(args[1])
	probeNum = int(args[2])


	probe = (name, width)

	print(printProbe(probe, probeNum))

if __name__ == '__main__':
	main(sys.argv[1:])