cvw/sim/wave-dos/peripheral-waves.do

# peripheral-waves.do 

restart -f
delete wave /*
view wave

# general stuff
add wave /testbench/clk
add wave /testbench/reset
add wave -divider

#add wave /testbench/dut/core/DataStall
add wave /testbench/dut/core/StallF
add wave /testbench/dut/core/StallD
add wave /testbench/dut/core/StallE
add wave /testbench/dut/core/StallM
add wave /testbench/dut/core/StallW
add wave /testbench/dut/core/FlushD
add wave /testbench/dut/core/FlushE
add wave /testbench/dut/core/FlushM
add wave /testbench/dut/core/FlushW
add wave -divider

add wave -hex /testbench/dut/core/ifu/PCF
add wave -hex /testbench/dut/core/ifu/PCD
add wave -hex /testbench/dut/core/ifu/InstrD
add wave -hex /testbench/dut/core/ieu/c/InstrValidD
add wave /testbench/InstrDName
add wave -divider
add wave -hex /testbench/dut/core/ifu/PCE
add wave -hex /testbench/dut/core/ifu/InstrE
add wave -hex /testbench/dut/core/ieu/c/InstrValidE
add wave /testbench/InstrEName
add wave -hex /testbench/dut/core/ieu/dp/SrcAE
add wave -hex /testbench/dut/core/ieu/dp/SrcBE
add wave -hex /testbench/dut/core/ieu/dp/ALUResultE
#add wave /testbench/dut/core/ieu/dp/PCSrcE
add wave /testbench/dut/core/mdu/genblk1/div/DivStartE
add wave /testbench/dut/core/mdu/DivBusyE
add wave -hex /testbench/dut/core/mdu/genblk1/div/RemM
add wave -hex /testbench/dut/core/mdu/genblk1/div/QuotM

add wave -divider
add wave -hex /testbench/dut/core/ifu/PCM
add wave -hex /testbench/dut/core/ifu/InstrM
add wave -hex /testbench/dut/core/ieu/c/InstrValidM
add wave /testbench/InstrMName
add wave /testbench/dut/uncore/uncore/ram/memwrite
add wave -hex /testbench/dut/core/WriteDataM
add wave -hex /testbench/dut/core/lsu.bus.dcache/MemPAdrM
add wave -hex /testbench/dut/core/lsu.bus.dcache/WriteDataM
add wave -hex /testbench/dut/core/lsu.bus.dcache/ReadDataM
add wave -divider
add wave -hex /testbench/PCW
#add wave -hex /testbench/InstrW
#add wave -hex /testbench/dut/core/ieu/c/InstrValidW
#add wave /testbench/InstrWName
add wave -hex /testbench/dut/core/ReadDataW
add wave -hex /testbench/dut/core/ieu/dp/ResultW
add wave -hex /testbench/dut/core/ieu/dp/RegWriteW
add wave -hex /testbench/dut/core/ieu/dp/WriteDataW
add wave -hex /testbench/dut/core/ieu/dp/RdW
add wave -divider
add wave -hex /testbench/dut/core/priv/csr/TrapM
add wave -hex /testbench/dut/core/priv/csr/UnalignedNextEPCM
add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEPCM
add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW

add wave -divider RegFile
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[1]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[2]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[3]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[4]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[5]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[6]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[7]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[8]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[9]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[10]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[11]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[12]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[13]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[14]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[15]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[16]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[17]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[18]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[19]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[20]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[21]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[22]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[23]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[24]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[25]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[26]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[27]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[28]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[29]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[30]
add wave -hex /testbench/dut/core/ieu/dp/regf/rf[31]

# peripherals
add wave -divider PLIC
add wave -hex /testbench/dut/core/priv/csr/TrapM
add wave -hex /testbench/dut/uncore/uncore/plic/plic/*
add wave -hex /testbench/dut/uncore/uncore/plic/plic/intPriority
add wave -hex /testbench/dut/uncore/uncore/plic/plic/pendingArray
add wave -divider UART
add wave -hex /testbench/dut/uncore/uncore/uart/uart/u/*
add wave -divider GPIO
add wave -hex /testbench/dut/uncore/uncore/gpio/gpio/*
#add wave -divider
#add wave -hex /testbench/dut/core/ebu/ebu/*
#add wave -divider
#add wave -divider

# everything else
add wave -hex -r /testbench/*
do script refactor 2021-04-24 13:32:09 +00:00			`# peripheral-waves.do`
refactored sim file 2021-03-05 19:25:16 +00:00
			`restart -f`
			`delete wave /*`
			`view wave`

Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 10:40:53 +00:00			`# general stuff`
refactored sim file 2021-03-05 19:25:16 +00:00			`add wave /testbench/clk`
			`add wave /testbench/reset`
			`add wave -divider`
Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 10:40:53 +00:00
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`#add wave /testbench/dut/core/DataStall`
			`add wave /testbench/dut/core/StallF`
			`add wave /testbench/dut/core/StallD`
			`add wave /testbench/dut/core/StallE`
			`add wave /testbench/dut/core/StallM`
			`add wave /testbench/dut/core/StallW`
			`add wave /testbench/dut/core/FlushD`
			`add wave /testbench/dut/core/FlushE`
			`add wave /testbench/dut/core/FlushM`
			`add wave /testbench/dut/core/FlushW`
refactored sim file 2021-03-05 19:25:16 +00:00			`add wave -divider`
Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 10:40:53 +00:00
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`add wave -hex /testbench/dut/core/ifu/PCF`
			`add wave -hex /testbench/dut/core/ifu/PCD`
			`add wave -hex /testbench/dut/core/ifu/InstrD`
			`add wave -hex /testbench/dut/core/ieu/c/InstrValidD`
refactored sim file 2021-03-05 19:25:16 +00:00			`add wave /testbench/InstrDName`
			`add wave -divider`
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`add wave -hex /testbench/dut/core/ifu/PCE`
			`add wave -hex /testbench/dut/core/ifu/InstrE`
			`add wave -hex /testbench/dut/core/ieu/c/InstrValidE`
refactored sim file 2021-03-05 19:25:16 +00:00			`add wave /testbench/InstrEName`
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`add wave -hex /testbench/dut/core/ieu/dp/SrcAE`
			`add wave -hex /testbench/dut/core/ieu/dp/SrcBE`
			`add wave -hex /testbench/dut/core/ieu/dp/ALUResultE`
			`#add wave /testbench/dut/core/ieu/dp/PCSrcE`
			`add wave /testbench/dut/core/mdu/genblk1/div/DivStartE`
			`add wave /testbench/dut/core/mdu/DivBusyE`
			`add wave -hex /testbench/dut/core/mdu/genblk1/div/RemM`
			`add wave -hex /testbench/dut/core/mdu/genblk1/div/QuotM`
Moved negating divider otuput to M stage 2021-10-02 14:03:02 +00:00
refactored sim file 2021-03-05 19:25:16 +00:00			`add wave -divider`
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`add wave -hex /testbench/dut/core/ifu/PCM`
			`add wave -hex /testbench/dut/core/ifu/InstrM`
			`add wave -hex /testbench/dut/core/ieu/c/InstrValidM`
refactored sim file 2021-03-05 19:25:16 +00:00			`add wave /testbench/InstrMName`
Added generate around uncore. 2022-08-25 15:35:24 +00:00			`add wave /testbench/dut/uncore/uncore/ram/memwrite`
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`add wave -hex /testbench/dut/core/WriteDataM`
			`add wave -hex /testbench/dut/core/lsu.bus.dcache/MemPAdrM`
			`add wave -hex /testbench/dut/core/lsu.bus.dcache/WriteDataM`
			`add wave -hex /testbench/dut/core/lsu.bus.dcache/ReadDataM`
refactored sim file 2021-03-05 19:25:16 +00:00			`add wave -divider`
Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 10:40:53 +00:00			`add wave -hex /testbench/PCW`
Moved negating divider otuput to M stage 2021-10-02 14:03:02 +00:00			`#add wave -hex /testbench/InstrW`
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`#add wave -hex /testbench/dut/core/ieu/c/InstrValidW`
Moved negating divider otuput to M stage 2021-10-02 14:03:02 +00:00			`#add wave /testbench/InstrWName`
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`add wave -hex /testbench/dut/core/ReadDataW`
			`add wave -hex /testbench/dut/core/ieu/dp/ResultW`
			`add wave -hex /testbench/dut/core/ieu/dp/RegWriteW`
			`add wave -hex /testbench/dut/core/ieu/dp/WriteDataW`
			`add wave -hex /testbench/dut/core/ieu/dp/RdW`
refactored sim file 2021-03-05 19:25:16 +00:00			`add wave -divider`
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`add wave -hex /testbench/dut/core/priv/csr/TrapM`
			`add wave -hex /testbench/dut/core/priv/csr/UnalignedNextEPCM`
			`add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEPCM`
			`add wave -hex /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW`
changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 16:27:15 +00:00
			`add wave -divider RegFile`
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[1]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[2]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[3]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[4]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[5]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[6]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[7]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[8]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[9]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[10]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[11]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[12]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[13]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[14]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[15]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[16]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[17]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[18]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[19]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[20]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[21]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[22]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[23]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[24]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[25]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[26]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[27]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[28]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[29]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[30]`
			`add wave -hex /testbench/dut/core/ieu/dp/regf/rf[31]`
Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 10:40:53 +00:00
			`# peripherals`
changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 16:27:15 +00:00			`add wave -divider PLIC`
Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00			`add wave -hex /testbench/dut/core/priv/csr/TrapM`
Added generate around uncore. 2022-08-25 15:35:24 +00:00			`add wave -hex /testbench/dut/uncore/uncore/plic/plic/*`
			`add wave -hex /testbench/dut/uncore/uncore/plic/plic/intPriority`
			`add wave -hex /testbench/dut/uncore/uncore/plic/plic/pendingArray`
changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 16:27:15 +00:00			`add wave -divider UART`
Added generate around uncore. 2022-08-25 15:35:24 +00:00			`add wave -hex /testbench/dut/uncore/uncore/uart/uart/u/*`
changed stop of linux boot from arch_cpu_idle to do_idle 2021-07-16 16:27:15 +00:00			`add wave -divider GPIO`
Added generate around uncore. 2022-08-25 15:35:24 +00:00			`add wave -hex /testbench/dut/uncore/uncore/gpio/gpio/*`
Reduced complexity of pmpadrdec 2021-06-23 07:03:52 +00:00			`#add wave -divider`
Added generate around ebu. 2022-08-25 14:24:13 +00:00			`#add wave -hex /testbench/dut/core/ebu/ebu/*`
Reduced complexity of pmpadrdec 2021-06-23 07:03:52 +00:00			`#add wave -divider`
			`#add wave -divider`
Yee hoo first draft of PLIC plus self-checking tests 2021-04-04 10:40:53 +00:00
			`# everything else`
refactored sim file 2021-03-05 19:25:16 +00:00			`add wave -hex -r /testbench/*`