forked from Github_Repos/cvw
128 lines
6.0 KiB
Systemverilog
128 lines
6.0 KiB
Systemverilog
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///////////////////////////////////////////
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// globalHistoryPredictor.sv
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//
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// Written: Shreya Sanghai
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// Email: ssanghai@hmc.edu
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// Created: March 16, 2021
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// Modified:
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//
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// Purpose: Global History Branch predictor with parameterized global history register
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module speculativeglobalhistory
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#(parameter int k = 10
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)
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(input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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// input logic [`XLEN-1:0] LookUpPC,
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output logic [1:0] DirPredictionF,
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output logic DirPredictionWrongE,
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// update
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
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input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
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input logic PCSrcE
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);
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logic MatchD, MatchE, MatchM, MatchW, MatchX, MatchXF;
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// logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW;
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logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
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logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW, NewDirPredictionX, NewDirPredictionXF;
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logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHRW, GHRNextF, GHRCurrentF, GHRCurrentE;
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logic [k-1:0] NewGHRF, NewGHRD, NewGHRE, NewGHRM, NewGHRW;
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logic PCSrcM, PCSrcW;
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logic [`XLEN-1:0] PCW;
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ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
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.ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
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.ra1(NewGHRF),
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.rd1(TableDirPredictionF),
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.wa2(GHRM),
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.wd2(NewDirPredictionM),
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.we2(BranchInstrM & ~StallM & ~FlushM),
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.bwe2(1'b1));
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// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the demi stage NextF and then
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// register for use in the Fetch stage.
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assign MatchD = BranchInstrD & (GHRD == GHRF);
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assign MatchE = BranchInstrE & (GHRE == GHRF);
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assign MatchM = BranchInstrM & (GHRM == GHRF);
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assign MatchW = BranchInstrW & (GHRW == GHRF);
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assign MatchX = MatchD | MatchE | MatchM | MatchW;
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assign NewDirPredictionX = MatchD ? NewDirPredictionD :
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MatchE ? NewDirPredictionE :
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MatchM ? NewDirPredictionM :
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MatchW ? NewDirPredictionW : '0;
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flopenr #(2) NewPredXReg(clk, reset, ~StallF, NewDirPredictionX, NewDirPredictionXF);
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flopenrc #(1) DoForwardReg(clk, reset, FlushD, ~StallF, MatchX, MatchXF);
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assign DirPredictionF = MatchXF ? NewDirPredictionXF : TableDirPredictionF;
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// DirPrediction pipeline
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flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
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flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
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// New prediction pipeline
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satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
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flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
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satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
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flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
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flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
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// PCSrc pipeline
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
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// GHR pipeline
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assign GHRNextF = FlushD & BranchInstrD & ~FlushE & ~FlushM & ~FlushW ? NewGHRD :
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FlushE & BranchInstrE & ~FlushM & ~FlushW ? NewGHRE :
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FlushM & BranchInstrM & ~FlushW ? NewGHRM :
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FlushW & BranchInstrW ? NewGHRW :
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NewGHRF;
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flopenr #(k) GHRFReg(clk, reset, ~StallF, GHRNextF, GHRF);
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//assign GHRF = BranchInstrF ? {NewDirPredictionF[1], GHRCurrentF[k-1:1]} : GHRCurrentF;
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assign NewGHRF = BranchInstrF ? {NewDirPredictionF[1], GHRF[k-1:1]} : GHRF;
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flopenr #(k) GHRDReg(clk, reset, ~StallD, GHRF, GHRD);
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assign NewGHRD = BranchInstrD ? {NewDirPredictionD[1], GHRD[k-1:1]} : GHRD;
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flopenr #(k) GHREReg(clk, reset, ~StallE, GHRD, GHRE);
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assign NewGHRE = BranchInstrE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
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flopenr #(k) GHRMReg(clk, reset, ~StallM, GHRE, GHRM);
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assign NewGHRM = BranchInstrM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
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flopenr #(k) GHRWReg(clk, reset, ~StallW, GHRM, GHRW);
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assign NewGHRW = BranchInstrW ? {PCSrcW, GHRW[k-1:1]} : GHRW;
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assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
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flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
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endmodule
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