forked from Github_Repos/cvw
46 lines
1.9 KiB
Systemverilog
46 lines
1.9 KiB
Systemverilog
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`include "wally-config.vh"
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// convert shift
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// fp -> int: | `XLEN zeros | Mantissa | 0's if nessisary | << CalcExp
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// process:
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// - start - CalcExp = 1 + XExp - Largest Bias
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// | `XLEN zeros | Mantissa | 0's if nessisary |
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//
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// - shift left 1 (1)
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// | `XLEN-1 zeros |bit| frac | 0's if nessisary |
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// . <- binary point
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//
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// - shift left till unbiased exponent is 0 (XExp - Largest Bias)
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// | 0's | Mantissa | 0's if nessisary |
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// | keep |
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//
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// fp -> fp:
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// - if result is denormalized or underflowed:
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// | `NF-1 zeros | Mantissa | 0's if nessisary | << NF+CalcExp-1
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// process:
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// - start
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// | mantissa | 0's |
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//
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// - shift right by NF-1 (NF-1)
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// | `NF-1 zeros | mantissa | 0's |
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//
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// - shift left by CalcExp = XExp - Largest bias + new bias
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// | 0's | mantissa | 0's |
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// | keep |
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//
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// - if the input is denormalized:
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// | lzcIn | 0's if nessisary | << ZeroCnt+1
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// - plus 1 to shift out the first 1
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//
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// int -> fp: | lzcIn | 0's if nessisary | << ZeroCnt+1
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// - plus 1 to shift out the first 1
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module normshift(
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input logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt, // normalization shift count
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input logic [`NORMSHIFTSZ-1:0] ShiftIn, // is the sum zero
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output logic [`NORMSHIFTSZ-1:0] Shifted // is the sum zero
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);
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assign Shifted = ShiftIn << ShiftAmt;
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endmodule
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