forked from Github_Repos/cvw
50 lines
2.0 KiB
ArmAsm
50 lines
2.0 KiB
ArmAsm
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///////////////////////////////////////////
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//
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// WALLY-privilege-interrupt-enable-stack
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//
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// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
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//
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// Created 2022-04-10
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-32.h"
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INIT_TESTS
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CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
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TRAP_HANDLER m, DEBUG=1
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li x28, 0x8
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csrs mstatus, x28 // set mstatus.MIE bit to 1
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WRITE_READ_CSR mie, 0xFFF
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// test 5.3.1.6 Interrupt enabling and priority tests
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// Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling
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jal cause_m_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
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li x28, 0x8
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csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen
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// attempt to cause interrupt, it should not go through
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jal cause_m_soft_interrupt
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END_TESTS
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TEST_STACK_AND_DATA
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