2021-01-15 04:37:51 +00:00
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///////////////////////////////////////////
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// csrs.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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2021-05-03 21:54:57 +00:00
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// dottolia@hmc.edu 3 May 2021 - fix bug with stvec getting wrong value
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2021-01-15 04:37:51 +00:00
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//
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// Purpose: Supervisor-Mode Control and Status Registers
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// See RISC-V Privileged Mode Specification 20190608
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//
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2023-01-11 22:03:44 +00:00
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// A component of the CORE-V Wally configurable RISC-V project.
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2021-01-15 04:37:51 +00:00
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//
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2023-01-10 19:35:20 +00:00
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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2021-01-15 04:37:51 +00:00
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//
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2023-01-10 19:35:20 +00:00
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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2021-01-15 04:37:51 +00:00
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//
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2023-01-10 19:35:20 +00:00
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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2021-01-15 04:37:51 +00:00
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//
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2023-01-10 19:35:20 +00:00
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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2022-01-07 12:58:40 +00:00
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////////////////////////////////////////////////////////////////////////////////////////////////
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2021-01-23 15:48:12 +00:00
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`include "wally-config.vh"
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2021-01-23 15:48:12 +00:00
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module csrs #(parameter
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// Supervisor CSRs
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SSTATUS = 12'h100,
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SIE = 12'h104,
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STVEC = 12'h105,
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SCOUNTEREN = 12'h106,
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SSCRATCH = 12'h140,
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SEPC = 12'h141,
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SCAUSE = 12'h142,
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STVAL = 12'h143,
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SIP= 12'h144,
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2021-06-11 03:47:32 +00:00
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SATP = 12'h180,
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// Constants
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ZERO = {(`XLEN){1'b0}},
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SEDELEG_MASK = ~(ZERO | `XLEN'b111 << 9)
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2021-04-20 21:57:56 +00:00
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) (
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2021-09-27 18:57:46 +00:00
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input logic clk, reset,
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2022-12-23 08:21:36 +00:00
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input logic InstrValidNotFlushedM,
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input logic CSRSWriteM, STrapM,
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input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, SSTATUS_REGW,
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input logic STATUS_TVM,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [1:0] PrivilegeModeW,
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2022-05-18 04:04:01 +00:00
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(* mark_debug = "true" *) output logic [`XLEN-1:0] CSRSReadValM, STVEC_REGW,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] SEPC_REGW,
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output logic [31:0] SCOUNTEREN_REGW,
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2021-03-05 06:22:53 +00:00
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output logic [`XLEN-1:0] SATP_REGW,
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2022-12-21 20:32:49 +00:00
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(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW, MIDELEG_REGW,
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output logic WriteSSTATUSM,
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output logic IllegalCSRSAccessM
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);
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// Supervisor mode CSRs sometimes supported
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2022-01-05 14:35:25 +00:00
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if (`S_SUPPORTED) begin:csrs
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logic WriteSTVECM;
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logic WriteSSCRATCHM, WriteSEPCM;
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logic WriteSCAUSEM, WriteSTVALM, WriteSATPM, WriteSCOUNTERENM;
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2022-01-18 23:29:21 +00:00
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(* mark_debug = "true" *) logic [`XLEN-1:0] SSCRATCH_REGW, STVAL_REGW;
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(* mark_debug = "true" *) logic [`XLEN-1:0] SCAUSE_REGW;
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2022-01-18 23:19:33 +00:00
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assign WriteSSTATUSM = CSRSWriteM & (CSRAdrM == SSTATUS) & InstrValidNotFlushedM;
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assign WriteSTVECM = CSRSWriteM & (CSRAdrM == STVEC) & InstrValidNotFlushedM;
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assign WriteSSCRATCHM = CSRSWriteM & (CSRAdrM == SSCRATCH) & InstrValidNotFlushedM;
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assign WriteSEPCM = STrapM | (CSRSWriteM & (CSRAdrM == SEPC)) & InstrValidNotFlushedM;
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assign WriteSCAUSEM = STrapM | (CSRSWriteM & (CSRAdrM == SCAUSE)) & InstrValidNotFlushedM;
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assign WriteSTVALM = STrapM | (CSRSWriteM & (CSRAdrM == STVAL)) & InstrValidNotFlushedM;
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assign WriteSATPM = CSRSWriteM & (CSRAdrM == SATP) & (PrivilegeModeW == `M_MODE | ~STATUS_TVM) & InstrValidNotFlushedM;
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assign WriteSCOUNTERENM = CSRSWriteM & (CSRAdrM == SCOUNTEREN) & InstrValidNotFlushedM;
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// CSRs
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2022-02-02 20:28:21 +00:00
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flopenr #(`XLEN) STVECreg(clk, reset, WriteSTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, STVEC_REGW);
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flopenr #(`XLEN) SSCRATCHreg(clk, reset, WriteSSCRATCHM, CSRWriteValM, SSCRATCH_REGW);
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flopenr #(`XLEN) SEPCreg(clk, reset, WriteSEPCM, NextEPCM, SEPC_REGW);
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flopenr #(`XLEN) SCAUSEreg(clk, reset, WriteSCAUSEM, NextCauseM, SCAUSE_REGW);
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flopenr #(`XLEN) STVALreg(clk, reset, WriteSTVALM, NextMtvalM, STVAL_REGW);
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2022-02-03 01:08:34 +00:00
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if (`VIRTMEM_SUPPORTED)
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flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
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else
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assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
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2022-02-02 20:28:21 +00:00
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flopens #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW);
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// CSR Reads
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always_comb begin:csrr
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IllegalCSRSAccessM = 0;
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case (CSRAdrM)
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SSTATUS: CSRSReadValM = SSTATUS_REGW;
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STVEC: CSRSReadValM = STVEC_REGW;
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2022-12-21 20:39:09 +00:00
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SIP: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW & 12'h222 & MIDELEG_REGW}; // only read supervisor fields
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2022-05-12 15:10:10 +00:00
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SIE: CSRSReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW & 12'h222}; // only read supervisor fields
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SSCRATCH: CSRSReadValM = SSCRATCH_REGW;
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SEPC: CSRSReadValM = SEPC_REGW;
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SCAUSE: CSRSReadValM = SCAUSE_REGW;
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STVAL: CSRSReadValM = STVAL_REGW;
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2022-02-03 01:08:34 +00:00
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SATP: if (`VIRTMEM_SUPPORTED & (PrivilegeModeW == `M_MODE | ~STATUS_TVM)) CSRSReadValM = SATP_REGW;
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else begin
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CSRSReadValM = 0;
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if (PrivilegeModeW == `S_MODE & STATUS_TVM) IllegalCSRSAccessM = 1;
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end
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SCOUNTEREN:CSRSReadValM = {{(`XLEN-32){1'b0}}, SCOUNTEREN_REGW};
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default: begin
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CSRSReadValM = 0;
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IllegalCSRSAccessM = 1;
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end
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endcase
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end
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end else begin
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assign WriteSSTATUSM = 0;
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assign CSRSReadValM = 0;
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assign SEPC_REGW = 0;
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assign STVEC_REGW = 0;
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assign SCOUNTEREN_REGW = 0;
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assign SATP_REGW = 0;
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assign IllegalCSRSAccessM = 1;
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end
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endmodule
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