forked from Github_Repos/cvw
64 lines
3.3 KiB
Systemverilog
64 lines
3.3 KiB
Systemverilog
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///////////////////////////////////////////
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// lrsc.sv
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//
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// Written: David_Harris@hmc.edu 17 July 2021
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// Modified:
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//
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// Purpose: Load Reserved / Store Conditional unit
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// Track the reservation and squash the store if it fails
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module lrsc
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(
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input logic clk, reset,
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input logic FlushW, StallWtoDCache,
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input logic MemReadM,
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input logic [1:0] MemRWMtoDCache, // *** how does this differ from MemReadM
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input logic [1:0] AtomicMtoDCache,
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input logic [`PA_BITS-1:0] MemPAdrM, // from mmu to dcache
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output logic SquashSCM,
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output logic SquashSCWfromDCache
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);
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// Handle atomic load reserved / store conditional
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generate
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if (`A_SUPPORTED) begin // atomic instructions supported
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logic [`PA_BITS-1:2] ReservationPAdrW;
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logic ReservationValidM, ReservationValidW;
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logic lrM, scM, WriteAdrMatchM;
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assign lrM = MemReadM && AtomicMtoDCache[0];
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assign scM = MemRWMtoDCache[0] && AtomicMtoDCache[0];
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assign WriteAdrMatchM = MemRWMtoDCache[0] && (MemPAdrM[`PA_BITS-1:2] == ReservationPAdrW) && ReservationValidW;
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assign SquashSCM = scM && ~WriteAdrMatchM;
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always_comb begin // ReservationValidM (next value of valid reservation)
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if (lrM) ReservationValidM = 1; // set valid on load reserve
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else if (scM || WriteAdrMatchM) ReservationValidM = 0; // clear valid on store to same address or any sc
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else ReservationValidM = ReservationValidW; // otherwise don't change valid
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end
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flopenrc #(`PA_BITS-2) resadrreg(clk, reset, FlushW, lrM, MemPAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
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flopenrc #(1) resvldreg(clk, reset, FlushW, lrM, ReservationValidM, ReservationValidW);
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flopenrc #(1) squashreg(clk, reset, FlushW, ~StallWtoDCache, SquashSCM, SquashSCWfromDCache);
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end else begin // Atomic operations not supported
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assign SquashSCM = 0;
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assign SquashSCWfromDCache = 0;
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end
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endgenerate
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endmodule
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