forked from Github_Repos/cvw
60 lines
2.6 KiB
Systemverilog
60 lines
2.6 KiB
Systemverilog
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///////////////////////////////////////////
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// atomic.sv
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//
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// Written: Ross Thompson ross1728@gmail.com January 31, 2022
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// Modified:
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//
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// Purpose: atomic data path.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module atomic (
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input logic clk,
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input logic reset, FlushW, CPUBusy,
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input logic [`XLEN-1:0] ReadDataM,
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input logic [`XLEN-1:0] WriteDataM,
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input logic [`PA_BITS-1:0] LSUPAdrM,
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input logic [6:0] LSUFunct7M,
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input logic [2:0] LSUFunct3M,
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input logic [1:0] LSUAtomicM,
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input logic [1:0] PreLSURWM,
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input logic IgnoreRequest,
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input logic DTLBMissM,
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output logic [`XLEN-1:0] FinalAMOWriteDataM,
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output logic SquashSCW,
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output logic [1:0] LSURWM);
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logic [`XLEN-1:0] AMOResult;
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logic MemReadM;
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amoalu amoalu(.srca(ReadDataM), .srcb(WriteDataM), .funct(LSUFunct7M), .width(LSUFunct3M[1:0]),
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.result(AMOResult));
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mux2 #(`XLEN) wdmux(WriteDataM, AMOResult, LSUAtomicM[1], FinalAMOWriteDataM);
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assign MemReadM = PreLSURWM[1] & ~(IgnoreRequest) & ~DTLBMissM;
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lrsc lrsc(.clk, .reset, .FlushW, .CPUBusy, .MemReadM, .PreLSURWM, .LSUAtomicM, .LSUPAdrM,
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.SquashSCW, .LSURWM);
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endmodule
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