cvw/tests/wally-riscv-arch-test/riscv-test-suite/rv32e_unratified/C/src/cli-01.S

// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.5.1
// timestamp : Wed Aug  4 06:39:00 2021 GMT
// usage     : riscv_ctg \
//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /home/bilalsakhawat/dev2/riscv-ctg/sample_cgfs/rv32ec.cgf \
//                  --base-isa rv32e \
//                  --randomize
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the c.li instruction of the RISC-V C extension for the cli covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32EC")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*E.*C.*) ;def RVTEST_E = True;def TEST_CASE_1=True;",cli)

RVTEST_SIGBASE( x4,signature_x4_1)

inst_0:
// rd==x15, imm_val == (-2**(6-1)), imm_val == -32
// opcode:c.li; dest:x15; immval:-0x20
TEST_CASE(x7, x15, -0x20, x4, 0, c.li x15, -0x20;)

inst_1:
// rd==x8, imm_val == 31, imm_val == (2**(6-1)-1)
// opcode:c.li; dest:x8; immval:0x1f
TEST_CASE(x7, x8, 0x1f, x4, 4, c.li x8, 0x1f;)

inst_2:
// rd==x13, imm_val == -17, 
// opcode:c.li; dest:x13; immval:-0x11
TEST_CASE(x7, x13, -0x11, x4, 8, c.li x13, -0x11;)

inst_3:
// rd==x6, imm_val == -9, 
// opcode:c.li; dest:x6; immval:-0x9
TEST_CASE(x7, x6, -0x9, x4, 12, c.li x6, -0x9;)

inst_4:
// rd==x2, imm_val == -5, 
// opcode:c.li; dest:x2; immval:-0x5
TEST_CASE(x7, x2, -0x5, x4, 16, c.li x2, -0x5;)

inst_5:
// rd==x12, imm_val == -3, 
// opcode:c.li; dest:x12; immval:-0x3
TEST_CASE(x7, x12, -0x3, x4, 20, c.li x12, -0x3;)

inst_6:
// rd==x1, imm_val == -2, 
// opcode:c.li; dest:x1; immval:-0x2
TEST_CASE(x7, x1, -0x2, x4, 24, c.li x1, -0x2;)

inst_7:
// rd==x14, imm_val == 16, 
// opcode:c.li; dest:x14; immval:0x10
TEST_CASE(x7, x14, 0x10, x4, 28, c.li x14, 0x10;)

inst_8:
// rd==x3, imm_val == 0, 
// opcode:c.li; dest:x3; immval:0x0
TEST_CASE(x7, x3, 0x0, x4, 32, c.li x3, 0x0;)

inst_9:
// rd==x5, imm_val == 8, 
// opcode:c.li; dest:x5; immval:0x8
TEST_CASE(x7, x5, 0x8, x4, 36, c.li x5, 0x8;)

inst_10:
// rd==x10, imm_val == 4, 
// opcode:c.li; dest:x10; immval:0x4
TEST_CASE(x7, x10, 0x4, x4, 40, c.li x10, 0x4;)

inst_11:
// rd==x0, imm_val == 2, 
// opcode:c.li; dest:x0; immval:0x2
TEST_CASE(x2, x0, 0, x4, 44, c.li x0, 0x2;)

inst_12:
// rd==x11, imm_val == 1, 
// opcode:c.li; dest:x11; immval:0x1
TEST_CASE(x2, x11, 0x1, x4, 48, c.li x11, 0x1;)
RVTEST_SIGBASE( x1,signature_x1_0)

inst_13:
// rd==x7, imm_val == -22, 
// opcode:c.li; dest:x7; immval:-0x16
TEST_CASE(x2, x7, -0x16, x1, 0, c.li x7, -0x16;)

inst_14:
// rd==x4, imm_val == 21, 
// opcode:c.li; dest:x4; immval:0x15
TEST_CASE(x2, x4, 0x15, x1, 4, c.li x4, 0x15;)

inst_15:
// rd==x9, 
// opcode:c.li; dest:x9; immval:0x0
TEST_CASE(x2, x9, 0x0, x1, 8, c.li x9, 0x0;)

inst_16:
// imm_val == 2, 
// opcode:c.li; dest:x10; immval:0x2
TEST_CASE(x2, x10, 0x2, x1, 12, c.li x10, 0x2;)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x4_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x4_1:
    .fill 13*(XLEN/32),4,0xdeadbeef


signature_x1_0:
    .fill 4*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END