forked from Github_Repos/cvw
71 lines
2.8 KiB
Systemverilog
71 lines
2.8 KiB
Systemverilog
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///////////////////////////////////////////
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// fpuhazard.sv
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//
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// Written: me@KatherineParry.com 19 May 2021
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// Modified:
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//
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// Purpose: Determine forwarding, stalls and flushes for the FPU
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module fpuhazard(
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input logic [4:0] Adr1, Adr2, Adr3,
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input logic FRegWriteE, FRegWriteM, FRegWriteW,
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input logic [4:0] RdE, RdM, RdW,
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input logic DivBusyM,
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input logic RegWriteD,
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input logic [2:0] FResultSelD, FResultSelE,
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// Stall outputs
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output logic FStallE,
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output logic [1:0] Input1MuxD, Input2MuxD,
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output logic Input3MuxD
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);
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always_comb begin
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// set ReadData as default
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Input1MuxD = 2'b00;
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Input2MuxD = 2'b00;
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Input3MuxD = 1'b0;
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FStallE = DivBusyM;
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if ((Adr1 == RdE) & (FRegWriteE | ((FResultSelE == 3'b110) & RegWriteD)))
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if (FResultSelE == 3'b110) Input1MuxD = 2'b11; // choose SrcAM
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else FStallE = 1'b1; // otherwise stall
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else if ((Adr1 == RdM) & FRegWriteM) Input1MuxD = 2'b01; // choose FPUResultDirW
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else if ((Adr1 == RdW) & FRegWriteW) Input1MuxD = 2'b11; // choose FPUResultDirE
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else if ((Adr2 == RdE) & FRegWriteE) FStallE = 1'b1;//***add a signals saying whether input 1, 2 or 3 are used
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else if ((Adr2 == RdM) & FRegWriteM) Input2MuxD = 2'b01; // choose FPUResultDirW
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else if ((Adr2 == RdW) & FRegWriteW) Input2MuxD = 2'b10; // choose FPUResultDirE
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else if ((Adr3 == RdE) & FRegWriteE) FStallE = 1'b1;
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else if ((Adr3 == RdM) & FRegWriteM) FStallE = 1'b1;
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else if ((Adr3 == RdW) & FRegWriteW) Input3MuxD = 1'b1; // choose FPUResultDirE
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end
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endmodule
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