forked from Github_Repos/cvw
75 lines
3.2 KiB
Systemverilog
75 lines
3.2 KiB
Systemverilog
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///////////////////////////////////////////
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// wally-pipelined.sv
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//
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// Written: David_Harris@hmc.edu 6 November 2020
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// Modified:
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//
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// Purpose: Top level module for pipelined processor and memories
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// Full RV32/64IC instruction set
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//
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// To Do:
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// Sort out terminology of faults, traps, interrputs, exceptions
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// Long names for instruction decoder
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// *Consitency in capitalizaiton
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// *Divide into many files
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// *Keep lint clean
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// *Put in git repo
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// Sort out memory map
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// *Automate testing based on MISA
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// Drop Funct3 from Controller pipeline if not needed
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// Finish exceptions & test
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// *Flushes caused by exceptions
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// Generate statements to reduce hardware for unneeded exception logic
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// *RET
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// *Status register
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// Misaligned instruction faults on other aults
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//
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//
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// Note: the CSRs do not support the following features
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//- Disabling portions of the instruction set with bits of the MISA register
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//- Changing from RV64 to RV32 by writing the SXL/UXL bits of the STATUS register
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// As of January 2020, virtual memory is not yet supported
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//
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// Reference MISA Values:
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// 104: C compressed
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-macros.sv"
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module wallypipelined #(parameter XLEN=32, MISA=0, ZCSR = 1, ZCOUNTERS = 1) (
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input logic clk, reset,
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output logic [XLEN-1:0] WriteDataM, DataAdrM,
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output logic [1:0] MemRWM);
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logic [XLEN-1:0] PCF, ReadDataM;
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logic [31:0] InstrF;
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logic [7:0] ByteMaskM;
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logic InstrAccessFaultF, DataAccessFaultM;
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logic TimerIntM, SwIntM; // from CLINT
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logic ExtIntM = 0; // not yet connected
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// instantiate processor and memories
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wallypipelinedhart #(XLEN, MISA, ZCSR, ZCOUNTERS) hart(
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clk, reset, PCF, InstrF, MemRWM, ByteMaskM, DataAdrM,
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WriteDataM, ReadDataM, TimerIntM, ExtIntM, SwIntM, InstrAccessFaultF, DataAccessFaultM);
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imem #(XLEN) imem(PCF, InstrF, InstrAccessFaultF);
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dmem #(XLEN) dmem(clk, reset, MemRWM, ByteMaskM, DataAdrM, WriteDataM, ReadDataM,
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DataAccessFaultM, TimerIntM, SwIntM);
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endmodule
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