forked from Github_Repos/cvw
61 lines
2.5 KiB
Systemverilog
61 lines
2.5 KiB
Systemverilog
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///////////////////////////////////////////
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// dmem.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Data memory
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-macros.sv"
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// *** need idiom to map onto cache RAM with byte writes
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// *** and use memread signal to reduce power when reads aren't needed
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module dmem #(parameter XLEN=32) (
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input logic clk, reset,
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input logic [1:0] MemRWM,
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input logic [7:0] ByteMaskM,
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input logic [XLEN-1:0] AdrM, WdM,
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output logic [XLEN-1:0] RdM,
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output logic AccessFaultM,
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output logic TimerIntM, SwIntM);
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logic [XLEN-1:0] RdTimM, RdClintM;
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logic TimEnM, ClintEnM;
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// Address decoding
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assign TimEnM = AdrM[31] & ~(|AdrM[30:19]); // 0x80000000 - 0x8007FFFF *** check top bits too
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assign ClintEnM = ~(|AdrM[XLEN-1:26]) & AdrM[25] & ~(|AdrM[24:16]); // 0x02000000-0x0200FFFF
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// tightly integrated memory
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dtim #(XLEN) dtim(clk, MemRWM & {2{TimEnM}}, ByteMaskM, AdrM[18:0], WdM, RdTimM);
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// memory-mapped I/O peripherals
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clint #(XLEN) clint(clk, reset, MemRWM & {2{ClintEnM}}, ByteMaskM, AdrM[15:0], WdM, RdClintM,
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TimerIntM, SwIntM);
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// *** add cache and interface to external memory & other peripherals
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// merge reads
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assign RdM = RdTimM | RdClintM;
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assign AccessFaultM = ~(|TimEnM | ClintEnM);
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endmodule
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