forked from Github_Repos/cvw
34 lines
1.9 KiB
Markdown
34 lines
1.9 KiB
Markdown
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This subdirectory contains synthesis scripts for use with Synopsys
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Design Compiler (DC). The scripts are separated into two distinct
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sections: user and technology setups. The technology setup is found
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in .synopsys_dc.setup file. Key items within this technology setup
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are the location of the PDK and standard cell libraries.
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We are using the Skywater Technology 130nm process for the synthesis.
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The Oklahoma State University standard-cell libraries for this process
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are located via the target_library keyword. There are currently three
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versions of the standard-cell libraries available (see
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http://stineje.github.io) for dowload locations. Currently, the TT 18
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track OSU standard-cell library is utilized.
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There are other useful elements within the technology setup file, as
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well. These include user information as well as search path
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information. Good tool flows usually rely on finding the right files
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correctly and having a search path set correctly is importantly.
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The user setup is found in two main areas. The scripts/ and hdl/
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directories. The scripts directory contains a basic DC synthesis Tcl
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script that is involved when synthesis is run. Please modify this
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synth.tcl file to add information about PPA and information about your
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design (e.g., top-level name, SV files). The SV is found within the
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hdl/ subdirectory. Just put all your synthesis-friendly files in this
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directory or allude to the correct location in the synthesis Tcl
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script.
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After synthesis completes, always check your synthesis log file that
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will be called synth.log. Good tool flow starts and ends with
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understanding what is happening during a specific part of the flow.
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This can only be done through interpreting what the Electronic Design
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Automation (EDA) tool is doing. So, always check this file for any
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possible warnings or errors after completion. All output of synthesis
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is found in the reports/ subdirectory.
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