forked from Github_Repos/cvw
111 lines
4.6 KiB
Systemverilog
111 lines
4.6 KiB
Systemverilog
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///////////////////////////////////////////
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// subwordwrite.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Masking and muxing for subword writes
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module subwordwrite (
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input logic [`XLEN-1:0] HRDATA,
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input logic [31:0] HADDR,
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input logic [2:0] HSIZE,
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input logic [`XLEN-1:0] HWDATAIN,
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output logic [`XLEN-1:0] HWDATA
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);
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logic [7:0] ByteM; // *** declare locally to generate as either 4 or 8 bits
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logic [15:0] HalfwordM;
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logic [`XLEN-1:0] WriteDataSubwordDuplicated;
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logic [7:0] ByteMaskM;
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generate
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if (`XLEN == 64) begin
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// Compute write mask
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always_comb
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case(HSIZE[1:0])
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2'b00: begin ByteMaskM = 8'b00000000; ByteMaskM[HADDR[2:0]] = 1; end // sb
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2'b01: case (HADDR[2:1])
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2'b00: ByteMaskM = 8'b00000011;
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2'b01: ByteMaskM = 8'b00001100;
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2'b10: ByteMaskM = 8'b00110000;
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2'b11: ByteMaskM = 8'b11000000;
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endcase
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2'b10: if (HADDR[2]) ByteMaskM = 8'b11110000;
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else ByteMaskM = 8'b00001111;
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2'b11: ByteMaskM = 8'b11111111;
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endcase
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// Handle subword writes
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always_comb
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case(HSIZE[1:0])
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2'b00: WriteDataSubwordDuplicated = {8{HWDATAIN[7:0]}}; // sb
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2'b01: WriteDataSubwordDuplicated = {4{HWDATAIN[15:0]}}; // sh
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2'b10: WriteDataSubwordDuplicated = {2{HWDATAIN[31:0]}}; // sw
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2'b11: WriteDataSubwordDuplicated = HWDATAIN; // sw
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endcase
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always_comb begin
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HWDATA=HRDATA;
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if (ByteMaskM[0]) HWDATA[7:0] = WriteDataSubwordDuplicated[7:0];
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if (ByteMaskM[1]) HWDATA[15:8] = WriteDataSubwordDuplicated[15:8];
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if (ByteMaskM[2]) HWDATA[23:16] = WriteDataSubwordDuplicated[23:16];
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if (ByteMaskM[3]) HWDATA[31:24] = WriteDataSubwordDuplicated[31:24];
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if (ByteMaskM[4]) HWDATA[39:32] = WriteDataSubwordDuplicated[39:32];
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if (ByteMaskM[5]) HWDATA[47:40] = WriteDataSubwordDuplicated[47:40];
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if (ByteMaskM[6]) HWDATA[55:48] = WriteDataSubwordDuplicated[55:48];
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if (ByteMaskM[7]) HWDATA[63:56] = WriteDataSubwordDuplicated[63:56];
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end
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end else begin // 32-bit
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// Compute write mask
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always_comb
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case(HSIZE[1:0])
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2'b00: begin ByteMaskM = 8'b0000; ByteMaskM[{1'b0, HADDR[1:0]}] = 1; end // sb
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2'b01: if (HADDR[1]) ByteMaskM = 8'b1100;
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else ByteMaskM = 8'b0011;
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2'b10: ByteMaskM = 8'b1111;
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default: ByteMaskM = 8'b111; // shouldn't happen
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endcase
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// Handle subword writes
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always_comb
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case(HSIZE[1:0])
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2'b00: WriteDataSubwordDuplicated = {4{HWDATAIN[7:0]}}; // sb
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2'b01: WriteDataSubwordDuplicated = {2{HWDATAIN[15:0]}}; // sh
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2'b10: WriteDataSubwordDuplicated = HWDATAIN; // sw
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default: WriteDataSubwordDuplicated = HWDATAIN; // shouldn't happen
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endcase
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always_comb begin
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HWDATA=HRDATA;
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if (ByteMaskM[0]) HWDATA[7:0] = WriteDataSubwordDuplicated[7:0];
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if (ByteMaskM[1]) HWDATA[15:8] = WriteDataSubwordDuplicated[15:8];
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if (ByteMaskM[2]) HWDATA[23:16] = WriteDataSubwordDuplicated[23:16];
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if (ByteMaskM[3]) HWDATA[31:24] = WriteDataSubwordDuplicated[31:24];
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end
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end
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endgenerate
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endmodule
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