forked from Github_Repos/cvw
59 lines
2.2 KiB
Systemverilog
59 lines
2.2 KiB
Systemverilog
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///////////////////////////////////////////
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// fdivsqrtfgen2.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Radix 2 F Addend Generator
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fdivsqrtfgen2 (
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input logic sp, sz,
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input logic [`DIVb+1:0] C,
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input logic [`DIVb:0] U, UM,
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output logic [`DIVb+3:0] F
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);
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logic [`DIVb+3:0] FP, FN, FZ;
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logic [`DIVb+3:0] SExt, SMExt, CExt;
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assign SExt = {3'b0, U};
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assign SMExt = {3'b0, UM};
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assign CExt = {2'b11, C}; // extend C from Q2.k to Q4.k
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// Generate for both positive and negative bits
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assign FP = ~(SExt << 1) & CExt;
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assign FN = (SMExt << 1) | (CExt & ~(CExt << 2));
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assign FZ = '0;
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// Choose which adder input will be used
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always_comb
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if (sp) F = FP;
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else if (sz) F = FZ;
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else F = FN;
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endmodule
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