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///////////////////////////////////////////
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// subwordwrite.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Masking and muxing for subword writes
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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2022-01-07 12:58:40 +00:00
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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2022-01-07 12:58:40 +00:00
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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2021-01-30 04:43:48 +00:00
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//
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2022-01-07 12:58:40 +00:00
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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2021-01-30 04:43:48 +00:00
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`include "wally-config.vh"
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module subwordwrite (
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input logic [2:0] LSUPAdrM,
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input logic [2:0] LSUFunct3M,
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input logic [`XLEN-1:0] FinalAMOWriteDataM,
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output logic [`XLEN-1:0] FinalWriteDataM,
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output logic [`XLEN/8-1:0] ByteMaskM
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);
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2022-03-11 00:13:35 +00:00
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logic [`XLEN-1:0] WriteDataSubwordDuplicated;
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2022-03-10 21:48:31 +00:00
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2022-03-11 00:50:03 +00:00
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swbytemask swbytemask(.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), .HADDRD(LSUPAdrM),
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.ByteMask(ByteMaskM));
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2022-01-05 16:25:08 +00:00
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if (`XLEN == 64) begin:sww
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// Handle subword writes
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always_comb
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case(LSUFunct3M[1:0])
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2'b00: WriteDataSubwordDuplicated = {8{FinalAMOWriteDataM[7:0]}}; // sb
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2'b01: WriteDataSubwordDuplicated = {4{FinalAMOWriteDataM[15:0]}}; // sh
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2'b10: WriteDataSubwordDuplicated = {2{FinalAMOWriteDataM[31:0]}}; // sw
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2'b11: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // sw
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endcase
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always_comb begin
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FinalWriteDataM='0;
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if (ByteMaskM[0]) FinalWriteDataM[7:0] = WriteDataSubwordDuplicated[7:0];
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if (ByteMaskM[1]) FinalWriteDataM[15:8] = WriteDataSubwordDuplicated[15:8];
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if (ByteMaskM[2]) FinalWriteDataM[23:16] = WriteDataSubwordDuplicated[23:16];
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if (ByteMaskM[3]) FinalWriteDataM[31:24] = WriteDataSubwordDuplicated[31:24];
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if (ByteMaskM[4]) FinalWriteDataM[39:32] = WriteDataSubwordDuplicated[39:32];
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if (ByteMaskM[5]) FinalWriteDataM[47:40] = WriteDataSubwordDuplicated[47:40];
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if (ByteMaskM[6]) FinalWriteDataM[55:48] = WriteDataSubwordDuplicated[55:48];
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if (ByteMaskM[7]) FinalWriteDataM[63:56] = WriteDataSubwordDuplicated[63:56];
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end
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2022-01-05 16:25:08 +00:00
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end else begin:sww // 32-bit
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// Handle subword writes
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always_comb
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case(LSUFunct3M[1:0])
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2'b00: WriteDataSubwordDuplicated = {4{FinalAMOWriteDataM[7:0]}}; // sb
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2'b01: WriteDataSubwordDuplicated = {2{FinalAMOWriteDataM[15:0]}}; // sh
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2'b10: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // sw
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default: WriteDataSubwordDuplicated = FinalAMOWriteDataM; // shouldn't happen
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endcase
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always_comb begin
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FinalWriteDataM='0;
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if (ByteMaskM[0]) FinalWriteDataM[7:0] = WriteDataSubwordDuplicated[7:0];
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if (ByteMaskM[1]) FinalWriteDataM[15:8] = WriteDataSubwordDuplicated[15:8];
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if (ByteMaskM[2]) FinalWriteDataM[23:16] = WriteDataSubwordDuplicated[23:16];
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if (ByteMaskM[3]) FinalWriteDataM[31:24] = WriteDataSubwordDuplicated[31:24];
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end
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end
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endmodule
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