forked from Github_Repos/cvw
58 lines
2.8 KiB
Systemverilog
58 lines
2.8 KiB
Systemverilog
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///////////////////////////////////////////
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// privpiperegs.sv
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//
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// Written: David_Harris@hmc.edu 12 May 2022
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// Modified:
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//
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// Purpose: Pipeline registers for early exceptions
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module privpiperegs (
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input logic clk, reset,
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input logic StallD, StallE, StallM,
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input logic FlushD, FlushE, FlushM,
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input logic InstrPageFaultF, InstrAccessFaultF,
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input logic IllegalIEUInstrFaultD, IllegalFPUInstrD,
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output logic IllegalFPUInstrE,
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output logic InstrPageFaultM, InstrAccessFaultM,
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output logic IllegalIEUInstrFaultM, IllegalFPUInstrM
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);
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logic InstrPageFaultD, InstrAccessFaultD;
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logic InstrPageFaultE, InstrAccessFaultE;
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logic IllegalIEUInstrFaultE;
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// pipeline fault signals
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flopenrc #(2) faultregD(clk, reset, FlushD, ~StallD,
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{InstrPageFaultF, InstrAccessFaultF},
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{InstrPageFaultD, InstrAccessFaultD});
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flopenrc #(4) faultregE(clk, reset, FlushE, ~StallE,
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{IllegalIEUInstrFaultD, InstrPageFaultD, InstrAccessFaultD, IllegalFPUInstrD},
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{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE});
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flopenrc #(4) faultregM(clk, reset, FlushM, ~StallM,
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{IllegalIEUInstrFaultE, InstrPageFaultE, InstrAccessFaultE, IllegalFPUInstrE},
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{IllegalIEUInstrFaultM, InstrPageFaultM, InstrAccessFaultM, IllegalFPUInstrM});
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endmodule
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