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cvw/sim/wave-all.do

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Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/reset
add wave -noupdate /testbench/memfilename
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/PCE
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/core/ifu/InstrE
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate -divider <NULL>
Added generate around ebu.
2022-08-25 14:24:13 +00:00
add wave -noupdate /testbench/dut/core/ebu/ebu/IReadF
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate /testbench/dut/core/DataStall
add wave -noupdate /testbench/dut/core/InstrStall
add wave -noupdate /testbench/dut/core/StallF
add wave -noupdate /testbench/dut/core/StallD
add wave -noupdate /testbench/dut/core/FlushD
add wave -noupdate /testbench/dut/core/FlushE
add wave -noupdate /testbench/dut/core/FlushM
add wave -noupdate /testbench/dut/core/FlushW
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate -divider <NULL>
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrF
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate /testbench/InstrFName
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrD
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate /testbench/InstrDName
add wave -noupdate -divider <NULL>
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/InstrD
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/RdD
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs1D
add wave -noupdate -expand -group {Decode Stage} /testbench/dut/core/ieu/dp/Rs2D
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rf
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a1
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a2
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/a3
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rd1
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/rd2
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/wd3
add wave -noupdate -expand -group RegFile /testbench/dut/core/ieu/dp/regf/we3
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate /testbench/dut/core/ieu/dp/PCSrcE
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate -divider <NULL>
add wave -noupdate /testbench/InstrMName
Added generate around uncore.
2022-08-25 15:35:24 +00:00
add wave -noupdate /testbench/dut/uncore/uncore/ram/memwrite
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATA
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate -divider <NULL>
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 19:25:07 +00:00
add wave -noupdate -radix hexadecimal /testbench/PCW
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate /testbench/InstrWName
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate /testbench/dut/core/ieu/dp/RegWriteW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdW
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate -divider <NULL>
add wave -noupdate -radix hexadecimal /testbench/clk
add wave -noupdate -radix hexadecimal /testbench/reset
add wave -noupdate -radix hexadecimal /testbench/test
add wave -noupdate -radix hexadecimal /testbench/i
add wave -noupdate -radix hexadecimal /testbench/errors
add wave -noupdate -radix hexadecimal /testbench/totalerrors
add wave -noupdate -radix hexadecimal /testbench/testadr
add wave -noupdate -radix hexadecimal /testbench/InstrW
add wave -noupdate -radix hexadecimal /testbench/meminit
add wave -noupdate -radix hexadecimal /testbench/HRDATAEXT
add wave -noupdate -radix hexadecimal /testbench/HREADYEXT
add wave -noupdate -radix hexadecimal /testbench/HRESPEXT
add wave -noupdate -radix hexadecimal /testbench/HADDR
add wave -noupdate -radix hexadecimal /testbench/HWDATA
add wave -noupdate -radix hexadecimal /testbench/HWRITE
add wave -noupdate -radix hexadecimal /testbench/HSIZE
add wave -noupdate -radix hexadecimal /testbench/HBURST
add wave -noupdate -radix hexadecimal /testbench/HPROT
add wave -noupdate -radix hexadecimal /testbench/HTRANS
add wave -noupdate -radix hexadecimal /testbench/HMASTLOCK
add wave -noupdate -radix hexadecimal /testbench/HCLK
add wave -noupdate -radix hexadecimal /testbench/HRESETn
add wave -noupdate -radix hexadecimal /testbench/GPIOPinsIn
add wave -noupdate -radix hexadecimal /testbench/GPIOPinsOut
add wave -noupdate -radix hexadecimal /testbench/GPIOPinsEn
add wave -noupdate -radix hexadecimal /testbench/UARTSin
add wave -noupdate -radix hexadecimal /testbench/UARTSout
add wave -noupdate -radix hexadecimal /testbench/dut/clk
add wave -noupdate -radix hexadecimal /testbench/dut/reset
add wave -noupdate -radix hexadecimal /testbench/dut/HRDATAEXT
add wave -noupdate -radix hexadecimal /testbench/dut/HREADYEXT
add wave -noupdate -radix hexadecimal /testbench/dut/HRESPEXT
add wave -noupdate -radix hexadecimal /testbench/dut/HCLK
add wave -noupdate -radix hexadecimal /testbench/dut/HRESETn
add wave -noupdate -radix hexadecimal /testbench/dut/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/HWDATA
add wave -noupdate -radix hexadecimal /testbench/dut/HWRITE
add wave -noupdate -radix hexadecimal /testbench/dut/HSIZE
add wave -noupdate -radix hexadecimal /testbench/dut/HBURST
add wave -noupdate -radix hexadecimal /testbench/dut/HPROT
add wave -noupdate -radix hexadecimal /testbench/dut/HTRANS
add wave -noupdate -radix hexadecimal /testbench/dut/HMASTLOCK
add wave -noupdate -radix hexadecimal /testbench/dut/GPIOPinsIn
add wave -noupdate -radix hexadecimal /testbench/dut/GPIOPinsOut
add wave -noupdate -radix hexadecimal /testbench/dut/GPIOPinsEn
add wave -noupdate -radix hexadecimal /testbench/dut/UARTSin
add wave -noupdate -radix hexadecimal /testbench/dut/UARTSout
add wave -noupdate -radix hexadecimal /testbench/dut/PCF
add wave -noupdate -radix hexadecimal /testbench/dut/InstrF
add wave -noupdate -radix hexadecimal /testbench/dut/HRDATA
add wave -noupdate -radix hexadecimal /testbench/dut/HREADY
add wave -noupdate -radix hexadecimal /testbench/dut/HRESP
add wave -noupdate -radix hexadecimal /testbench/dut/InstrAccessFaultF
add wave -noupdate -radix hexadecimal /testbench/dut/DataAccessFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/TimerIntM
add wave -noupdate -radix hexadecimal /testbench/dut/SwIntM
add wave -noupdate -radix hexadecimal /testbench/dut/ExtIntM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/PCF
add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrF
add wave -noupdate -radix hexadecimal /testbench/dut/core/TimerIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ExtIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/SwIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrAccessFaultF
add wave -noupdate -radix hexadecimal /testbench/dut/core/DataAccessFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/HRDATA
add wave -noupdate -radix hexadecimal /testbench/dut/core/HREADY
add wave -noupdate -radix hexadecimal /testbench/dut/core/HRESP
add wave -noupdate -radix hexadecimal /testbench/dut/core/HCLK
add wave -noupdate -radix hexadecimal /testbench/dut/core/HRESETn
add wave -noupdate -radix hexadecimal /testbench/dut/core/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/core/HWDATA
add wave -noupdate -radix hexadecimal /testbench/dut/core/HWRITE
add wave -noupdate -radix hexadecimal /testbench/dut/core/HSIZE
add wave -noupdate -radix hexadecimal /testbench/dut/core/HBURST
add wave -noupdate -radix hexadecimal /testbench/dut/core/HPROT
add wave -noupdate -radix hexadecimal /testbench/dut/core/HTRANS
add wave -noupdate -radix hexadecimal /testbench/dut/core/HMASTLOCK
add wave -noupdate -radix hexadecimal /testbench/dut/core/ForwardAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ForwardBE
add wave -noupdate -radix hexadecimal /testbench/dut/core/StallF
add wave -noupdate -radix hexadecimal /testbench/dut/core/StallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/FlushD
add wave -noupdate -radix hexadecimal /testbench/dut/core/FlushE
add wave -noupdate -radix hexadecimal /testbench/dut/core/FlushM
add wave -noupdate -radix hexadecimal /testbench/dut/core/FlushW
add wave -noupdate -radix hexadecimal /testbench/dut/core/RetM
add wave -noupdate -radix hexadecimal /testbench/dut/core/TrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/CSRWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/PrivilegedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/SrcAM
add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrD
add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/PCE
add wave -noupdate -radix hexadecimal /testbench/dut/core/PCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/PCLinkW
add wave -noupdate -radix hexadecimal /testbench/dut/core/PCTargetE
add wave -noupdate -radix hexadecimal /testbench/dut/core/CSRReadValW
add wave -noupdate -radix hexadecimal /testbench/dut/core/PrivilegedNextPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/MemRWM
add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrValidM
add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/DataMisalignedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/IllegalBaseInstrFaultD
add wave -noupdate -radix hexadecimal /testbench/dut/core/IllegalIEUInstrFaultD
add wave -noupdate -radix hexadecimal /testbench/dut/core/LoadMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/LoadAccessFaultM
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 23:11:27 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/StoreAmoMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/StoreAmoAccessFaultM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrMisalignedAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/zero
add wave -noupdate -radix hexadecimal /testbench/dut/core/PCSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/CSRWritePendingDEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/LoadStallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/SetFflagsM
add wave -noupdate -radix hexadecimal /testbench/dut/core/FRM_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/FRegWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/MemRWAlignedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/Funct3M
add wave -noupdate -radix hexadecimal /testbench/dut/core/MemAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/MemPAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/WriteDataM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ReadDataM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ReadDataW
add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrPAdrF
add wave -noupdate -radix hexadecimal /testbench/dut/core/DataStall
add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrStall
add wave -noupdate -radix hexadecimal /testbench/dut/core/InstrAckD
add wave -noupdate -radix hexadecimal /testbench/dut/core/MemAckW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/StallF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/StallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/FlushD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/FlushE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/FlushM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/FlushW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrPAdrF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrStall
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCTargetE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/RetM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/TrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PrivilegedNextPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/IllegalBaseInstrFaultD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/IllegalIEUInstrFaultD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/UnalignedPCNextF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCNextF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/misaligned
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/BranchMisalignedFaultE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/BranchMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/TrapMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/StallExceptResolveBranchesF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PrivilegedChangePCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/IllegalCompInstrD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPlusUpperF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPlus2or4F
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCD
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-30 19:25:07 +00:00
add wave -noupdate -radix hexadecimal /testbench/PCW
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCLinkM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/CompressedF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrRawD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/nop
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/d0
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/d1
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/d2
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/s
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcmux/y
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/load
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/val
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/pcreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/load
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/val
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrDReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCDReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/InstrRawD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/InstrD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/IllegalCompInstrD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/instr16
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rds1
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rs2
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rs1p
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rs2p
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rds1p
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/rdp
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCILSP
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCILSPD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCSS
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCSSD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCL
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCLD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCI
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCS
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCSD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCB
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCIASP
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCIW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCJ
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immCILUI
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/immSH
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/decomp/op
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalginedReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMisalignedAdrReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrEReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrEReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrEReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrEReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/InstrMReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCEReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCEReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCEReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCEReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCMReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCMReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCMReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCMReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCWReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCWReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCWReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCWReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPDReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPDReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPDReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPDReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPEReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPEReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPEReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPEReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPMReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPMReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPMReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPMReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPWReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPWReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPWReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ifu/PCPWReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/InstrD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/IllegalIEUInstrFaultD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/IllegalBaseInstrFaultD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/PCE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/PCTargetE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/DataMisalignedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/DataAccessFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/MemRWM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/MemAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/WriteDataM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/SrcAM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/Funct3M
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ReadDataW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/CSRReadValW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/PCLinkW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/InstrValidM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/StallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/FlushD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/FlushE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/FlushM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/FlushW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RetM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/TrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/LoadStallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/PCSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/CSRWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/PrivilegedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/CSRWritePendingDEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ImmSrcD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/FlagsE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ALUControlE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ALUSrcAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ALUSrcBE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ResultSrcW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/TargetSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/Rs1D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/Rs2D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/Rs1E
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/Rs2E
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RdE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RdM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RdW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ForwardAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/ForwardBE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RegWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/RegWriteW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/MemReadE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/OpD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/Funct3D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/Funct7b5D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ImmSrcD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/StallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/FlushD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/IllegalIEUInstrFaultD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/IllegalBaseInstrFaultD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/FlushE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/FlagsE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/PCSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUControlE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUSrcAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUSrcBE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/TargetSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/MemReadE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/FlushM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/DataMisalignedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/MemRWM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/CSRWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/PrivilegedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/Funct3M
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/RegWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/FlushW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/RegWriteW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ResultSrcW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/CSRWritePendingDEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/RegWriteD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/RegWriteE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ResultSrcD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ResultSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ResultSrcM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/MemRWD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/MemRWE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/JumpD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/JumpE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/BranchD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/BranchE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUOpD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUControlD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUSrcAD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ALUSrcBD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/TargetSrcD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/W64D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/CSRWriteD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/CSRWriteE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/Funct3E
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/InstrValidM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/PrivilegedD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/PrivilegedE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ControlsD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/aluc3D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/subD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/sraD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/sltD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/sltuD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/BranchTakenE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/zeroE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ltE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/ltuE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregE/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregE/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregE/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregE/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregE/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregM/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregM/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregM/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregM/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregM/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregW/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregW/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregW/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregW/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/c/controlregW/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/StallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlushD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmSrcD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/InstrD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlushE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ForwardAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ForwardBE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/PCSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUControlE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUSrcAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUSrcBE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/TargetSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/PCE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlagsE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/PCTargetE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlushM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Funct3M
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/CSRReadValW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ReadDataW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RetM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/TrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/MemAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/FlushW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RegWriteW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultSrcW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/PCLinkW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1E
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2E
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2D
Changing signal name to ImmExtD/E to match figures Changing signal name: ExtImmD/E -> ImmExtD/E to match figures.
2023-01-17 14:33:58 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtD
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1E
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2E
Changing signal name to ImmExtD/E to match figures Changing signal name: ExtImmD/E -> ImmExtD/E to match figures.
2023-01-17 14:33:58 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtE
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ForwardedSrcAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcBE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/TargetBaseE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/IntResultW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ResultW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/we3
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/a1
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/a2
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/a3
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/wd3
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/rd1
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/rd2
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/regf/i
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ext/InstrD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ext/ImmSrcD
Changing signal name to ImmExtD/E to match figures Changing signal name: ExtImmD/E -> ImmExtD/E to match figures.
2023-01-17 14:33:58 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ext/ImmExtD
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD1EReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RD2EReg/q
Changing signal name to ImmExtD/E to match figures Changing signal name: ExtImmD/E -> ImmExtD/E to match figures.
2023-01-17 14:33:58 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ImmExtEReg/q
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs1EReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/Rs2EReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdEReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/d0
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/d1
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/d2
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/s
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/faemux/y
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/d0
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/d1
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/d2
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/s
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/fbemux/y
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/d0
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/d1
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/s
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcamux/y
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/d0
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/d1
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/s
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/srcbmux/y
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/A
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/B
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/ALUControl
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/Result
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/FlagsE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/a
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/amt
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/right
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/arith
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/w64
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/y
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/z
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/zshift
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/ylower
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/yupper
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/offset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/alu/sh/genblk1/amt6
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/d0
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/d1
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/s
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/targetsrcmux/y
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/SrcAMReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultMReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/WriteDataMReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdMEg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/ALUResultWReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/RdWEg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d0
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d1
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d2
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/d3
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/s
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/dp/resultmux/y
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs1D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs2D
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs1E
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/Rs2E
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RdE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RdM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RdW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/MemReadE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RegWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/RegWriteW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/ForwardAE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/ForwardBE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ieu/fw/LoadStallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/FlushW
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/DataStall
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemRWM
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/Funct3M
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataM
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/WriteDataM
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemPAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemRWAlignedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/DataMisalignedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/MemAckW
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataW
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/DataAccessFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/LoadMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/LoadAccessFaultM
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 23:11:27 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/StoreAmoMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/StoreAmoAccessFaultM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/dmem/ReadDataWReg/q
Added generate around ebu.
2022-08-25 14:24:13 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/UnsignedLoadM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/InstrPAdrF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IReadF
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IRData
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/MemPAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DReadM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/WriteDataM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DSizeM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DRData
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRDATA
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HREADY
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRESP
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HCLK
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRESETn
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HWDATA
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HWRITE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HSIZE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HBURST
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HPROT
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HTRANS
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HMASTLOCK
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/InstrAckD
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/MemAckW
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/GrantData
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/ISize
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/HRDATAMasked
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/IReady
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/DReady
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HRDATA
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/UnsignedLoadM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HSIZE
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HRDATAMasked
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/ByteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/HalfwordM
add wave -noupdate -radix hexadecimal /testbench/dut/core/ebu/ebu/swr/genblk1/WordM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/PCSrcE
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/CSRWritePendingDEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/RetM
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/TrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/LoadStallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/InstrStall
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/DataStall
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallF
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushD
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushE
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushM
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/FlushW
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/BranchFlushDE
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallDCause
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallFCause
add wave -noupdate -radix hexadecimal /testbench/dut/core/hzu/StallWCause
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/CSRWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SrcAM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/CSRReadValW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PrivilegedNextPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/RetM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/TrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrValidM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FRegWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadStallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PrivilegedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultF
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalIEUInstrFaultD
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadAccessFaultM
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 23:11:27 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StoreAmoMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StoreAmoAccessFaultM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/TimerIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/ExtIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SwIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrMisalignedAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MemAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SetFflagsM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FRM_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushD
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/FlushM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/NextPrivilegeModeM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/PrivilegeModeW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/CauseM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/NextFaultMtvalM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/UEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/UTVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MTVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MEDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MIDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SEDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/SIDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/uretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/sretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/mretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/ecallM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/ebreakM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/wfiM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/sfencevmaM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalCSRAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalIEUInstrFaultE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalIEUInstrFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultD
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrAccessFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/IllegalInstrFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/BreakpointFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/EcallFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/InstrPageFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/LoadPageFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/StorePageFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MTrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/UTrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_MPP
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_SPP
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_TSR
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_MIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/STATUS_SIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/MIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/md
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/sd
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/privmodereg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/privmodereg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/privmodereg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/InstrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/PrivilegedM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalIEUInstrFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalCSRAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/PrivilegeModeW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/STATUS_TSR
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalInstrFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/uretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/sretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/mretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/ecallM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/ebreakM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/wfiM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/sfencevmaM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/pmd/IllegalPrivilegedInstrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/FlushW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/InstrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/PCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SrcAM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/TrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MTrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UTrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/mretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/sretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/uretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/TimerIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/ExtIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SwIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/InstrValidM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/FRegWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/LoadStallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextPrivilegeModeM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/PrivilegeModeW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CauseM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextFaultMtvalM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_MPP
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_SPP
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_TSR
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UTVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MTVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MEDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MIDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SEDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_MIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/STATUS_SIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SetFflagsM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/FRM_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRReadValW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRMReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRSReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRUReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRNReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRCReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRSrcM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRRWM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRRSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRRCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRWriteValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MSTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SSTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/USTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTINHIBIT_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/MCOUNTEREN_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SCOUNTEREN_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/WriteMSTATUSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/WriteSSTATUSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/WriteUSTATUSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRMWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRSWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSRUWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UnalignedNextEPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextEPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextCauseM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/NextMtvalM
Renamed signals in the cache.
2022-11-29 16:52:40 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/CSCAdrM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/SIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/UIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRCAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRMAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRSAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRUAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/IllegalCSRNAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/InsufficientCSRPrivilegeM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRMWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRSWriteM
Renamed signals in the cache.
2022-11-29 16:52:40 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSCAdrM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/ExtIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/TimerIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SwIntM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/CSRWriteValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/IntInM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/IP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/IE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/MIP_WRITE_MASK
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/SIP_WRITE_MASK
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteMIPM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteMIEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteSIPM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csri/WriteSIEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/WriteMSTATUSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/WriteSSTATUSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/WriteUSTATUSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/TrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/FRegWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/NextPrivilegeModeM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/PrivilegeModeW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/mretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/sretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/uretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/CSRWriteValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/MSTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/SSTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/USTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPP
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SPP
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_TSR
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SD
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_TW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_TVM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MXR
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SUM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SUM_INT
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPRV
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPRV_INT
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SXL
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_UXL
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_XS
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_FS
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_FS_INT
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPP_NEXT
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_MPIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_SPIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_UPIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrsr/STATUS_UIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/InstrValidM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/LoadStallD
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRMWriteM
Renamed signals in the cache.
2022-11-29 16:52:40 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSCAdrM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/PrivilegeModeW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRWriteValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/MCOUNTINHIBIT_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/MCOUNTEREN_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/SCOUNTEREN_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/CSRCReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/IllegalCSRCAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CYCLE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER3_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER4_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CYCLEPlusM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/INSTRETPlusM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER3PlusM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/HPMCOUNTER4PlusM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextCYCLEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextINSTRETM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextHPMCOUNTER3M
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/NextHPMCOUNTER4M
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteCYCLEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteINSTRETM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteHPMCOUNTER3M
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/WriteHPMCOUNTER4M
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/CounterNumM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/CYCLEreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/INSTRETreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER3reg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/counters/genblk1/genblk1/HPMCOUNTER4reg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRMWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTrapM
Renamed signals in the cache.
2022-11-29 16:52:40 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSCAdrM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextEPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextCauseM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/NextMtvalM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRWriteValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/CSRMReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTEREN_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBIT_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMSTATUSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/IllegalCSRMAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISA_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCH_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVAL_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG01_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPCFG23_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/zero
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/allones
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEDELEG_MASK
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MIDELEG_MASK
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMTVECM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEDELEGM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMIDELEGM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMSCRATCHM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMEPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMCAUSEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMTVALM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMCOUNTERENM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WriteMCOUNTINHIBITM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WritePMPCFG0M
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WritePMPCFG2M
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/WritePMPADDR0M
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MISAbits
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG01reg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk2/PMPCFG23reg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/load
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/val
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MEDELEGreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/load
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/val
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/genblk1/MIDELEGreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/load
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/val
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVECreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MSCRATCHreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MEPCreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCAUSEreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MTVALreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/load
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/val
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTERENreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/load
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/val
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/MCOUNTINHIBITreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrm/PMPADDR0reg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRSWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STrapM
Renamed signals in the cache.
2022-11-29 16:52:40 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSCAdrM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextEPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextCauseM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/NextMtvalM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SSTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRWriteValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/CSRSReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/STVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SCOUNTEREN_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIDELEG_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/WriteSSTATUSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/IllegalCSRSAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/zero
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/allones
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/SEDELEG_MASK
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSTVECM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSEDELEGM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSIDELEGM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSSCRATCHM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSEPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSCAUSEM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSTVALM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSATPM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/WriteSCOUNTERENM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCH_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVAL_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/load
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/val
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVECreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SSCRATCHreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SEPCreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/load
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/val
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCAUSEreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/STVALreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SATPreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/load
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/val
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrs/genblk1/SCOUNTERENreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRNWriteM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTrapM
Renamed signals in the cache.
2022-11-29 16:52:40 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSCAdrM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextEPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextCauseM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/NextMtvalM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/USTATUS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRWriteValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/CSRNReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UTVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/UIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/WriteUSTATUSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csrn/IllegalCSRNAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRUWriteM
Renamed signals in the cache.
2022-11-29 16:52:40 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSCAdrM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRWriteValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/CSRUReadValM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/SetFflagsM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/FRM_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/IllegalCSRUAccessM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGS_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/WriteFFLAGSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/WriteFRMM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/WriteFCSRM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/NextFRMM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/NextFFLAGSM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FRMreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/csru/genblk1/FFLAGSreg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/csr/genblk1/CSRValWReg/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/en
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregD/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregE/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/clk
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/clear
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/d
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/faultregM/q
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/reset
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrMisalignedFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrAccessFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/IllegalInstrFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/BreakpointFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadMisalignedFaultM
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 23:11:27 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StoreAmoMisalignedFaultM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadAccessFaultM
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 23:11:27 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StoreAmoAccessFaultM
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/EcallFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrPageFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/LoadPageFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/StorePageFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/mretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/sretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/uretM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/PrivilegeModeW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/NextPrivilegeModeM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/SEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/UEPC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/UTVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MTVEC_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MIP_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MIE_REGW
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STATUS_MIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STATUS_SIE
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrMisalignedAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MemAdrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InstrM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/TrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MTrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/STrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/UTrapM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/RetM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/PrivilegedNextPCM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/CauseM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/NextFaultMtvalM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/MIntGlobalEnM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/SIntGlobalEnM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/PendingIntsM
add wave -noupdate -radix hexadecimal /testbench/dut/core/priv/trap/InterruptM
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/imem/AdrF
add wave -noupdate -radix hexadecimal /testbench/dut/imem/InstrF
add wave -noupdate -radix hexadecimal /testbench/dut/imem/InstrAccessFaultF
add wave -noupdate -radix hexadecimal /testbench/dut/imem/adrbits
add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd
add wave -noupdate -radix hexadecimal /testbench/dut/imem/rd2
Added generate around uncore.
2022-08-25 15:35:24 +00:00
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HCLK
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESETn
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATAIN
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWRITE
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSIZE
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HBURST
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HPROT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HTRANS
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HMASTLOCK
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRDATAEXT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYEXT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPEXT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRDATA
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADY
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESP
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/DataAccessFaultM
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/TimerIntM
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/SwIntM
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsIn
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsOut
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/GPIOPinsEn
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTSin
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTSout
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HWDATA
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADTim
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADCLINT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADGPIO
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADUART
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELTim
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELCLINT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELGPIO
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/PreHSELUART
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HSELUART
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPTim
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPCLINT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPGPIO
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HRESPUART
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYTim
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYCLINT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYGPIO
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/HREADYUART
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRW
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWtim
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWclint
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWgpio
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/MemRWuart
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/UARTIntr
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/Base
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/Range
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/HSEL
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/timdec/match
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/Base
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/Range
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/HSEL
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clintdec/match
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/Base
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/Range
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/HSEL
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpiodec/match
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/Base
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/Range
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/HSEL
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uartdec/match
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HRDATA
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HSIZE
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HWDATAIN
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HWDATA
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/ByteM
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/HalfwordM
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/WriteDataSubwordDuplicated
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/sww/ByteMaskM
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HCLK
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HRESETn
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/MemRWtim
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HWDATA
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HSELTim
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HREADTim
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HRESPTim
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/HREADYTim
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/entry
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/memread
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/memwrite
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/ram/busycount
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HCLK
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HRESETn
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MemRWclint
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HWDATA
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HREADCLINT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HRESPCLINT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/HREADYCLINT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/TimerIntM
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/SwIntM
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MTIMECMP
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MTIME
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/MSIP
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/entry
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/memread
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/clint/memwrite
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HCLK
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HRESETn
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/MemRWgpio
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HWDATA
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HREADGPIO
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HRESPGPIO
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/HREADYGPIO
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsIn
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsOut
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/GPIOPinsEn
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/INPUT_VAL
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/INPUT_EN
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/OUTPUT_EN
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/OUTPUT_VAL
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/entry
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/memread
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/gpio/memwrite
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HCLK
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HRESETn
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MemRWuart
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HADDR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HWDATA
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HREADUART
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HRESPUART
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/HREADYUART
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/SIN
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DSRb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DCDb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/CTSb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RIb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/SOUT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RTSb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/DTRb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/OUT1b
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/OUT2b
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/INTR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/TXRDYb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/RXRDYb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/A
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MEMRb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/MEMWb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/Din
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/Dout
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/BAUDOUTb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/HCLK
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/HRESETn
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/A
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/Din
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/Dout
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MEMRb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MEMWb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/INTR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/TXRDYb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RXRDYb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/BAUDOUTb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RCLK
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SIN
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SOUT
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RTSb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DTRb
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/OUT1b
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/OUT2b
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RBR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/FCR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/LCR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/LSR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SCR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLL
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLM
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/IER
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MSR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/MCR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SINd
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRbd
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDbd
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSbd
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIbd
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SINsync
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRbsync
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDbsync
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSbsync
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIbsync
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DSRb2
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DCDb2
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/CTSb2
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RIb2
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/SOUTbit
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/loop
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/DLAB
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/baudpulse
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbaudpulse
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbaudpulse
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/baudcount
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxoversampledcnt
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txoversampledcnt
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbitsreceived
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbitssent
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxstate
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txstate
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxshiftreg
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifohead
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotail
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifohead
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifotail
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotriggerlevel
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifoentries
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifoentries
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbitsexpected
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txbitsexpected
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/RXBR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxtimeoutcnt
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxcentered
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparity
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparitybit
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxstopbit
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxparityerr
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxoverrunerr
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxframingerr
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxbreak
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifohaserr
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdataready
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifoempty
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotriggered
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifotimeout
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfifodmaready
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdata9
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdata
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxerrbit
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxfullbit
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/TXHR
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txdata
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/nexttxdata
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txsr
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txnextbit
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txhrfull
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txsrfull
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txparity
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifoempty
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifofull
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txfifodmaready
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/fifoenabled
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/fifodmamodesel
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/evenparitysel
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxlinestatusintr
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/rxdataavailintr
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/txhremptyintr
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/modemstatusintr
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/intrpending
add wave -noupdate -radix hexadecimal /testbench/dut/uncore/uncore/uart/u/intrid
Added FlushF to hazard unit. Fixed some typos with the names of signals in the branch predictor. They were causing signals to be not set. Note there is a modelsim flag which prevents it from compiling if a logic is undefined. I will look this up and add it to the compiler.
2021-02-19 22:36:51 +00:00
add wave -noupdate -radix hexadecimal /testbench/it/clk
add wave -noupdate -radix hexadecimal /testbench/it/reset
add wave -noupdate -radix hexadecimal /testbench/it/FlushE
add wave -noupdate -radix hexadecimal /testbench/it/InstrD
add wave -noupdate -radix hexadecimal /testbench/it/InstrE
add wave -noupdate -radix hexadecimal /testbench/it/InstrM
add wave -noupdate -radix hexadecimal /testbench/it/InstrW
add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/clk
add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/reset
add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/d
add wave -noupdate -radix hexadecimal /testbench/it/InstrWReg/q
add wave -noupdate -radix hexadecimal /testbench/it/ddec/instr
add wave -noupdate -radix hexadecimal /testbench/it/ddec/op
add wave -noupdate -radix hexadecimal /testbench/it/ddec/funct3
add wave -noupdate -radix hexadecimal /testbench/it/ddec/funct7
add wave -noupdate -radix hexadecimal /testbench/it/ddec/imm
add wave -noupdate -radix hexadecimal /testbench/it/edec/instr
add wave -noupdate -radix hexadecimal /testbench/it/edec/op
add wave -noupdate -radix hexadecimal /testbench/it/edec/funct3
add wave -noupdate -radix hexadecimal /testbench/it/edec/funct7
add wave -noupdate -radix hexadecimal /testbench/it/edec/imm
add wave -noupdate -radix hexadecimal /testbench/it/mdec/instr
add wave -noupdate -radix hexadecimal /testbench/it/mdec/op
add wave -noupdate -radix hexadecimal /testbench/it/mdec/funct3
add wave -noupdate -radix hexadecimal /testbench/it/mdec/funct7
add wave -noupdate -radix hexadecimal /testbench/it/mdec/imm
add wave -noupdate -radix hexadecimal /testbench/it/wdec/instr
add wave -noupdate -radix hexadecimal /testbench/it/wdec/op
add wave -noupdate -radix hexadecimal /testbench/it/wdec/funct3
add wave -noupdate -radix hexadecimal /testbench/it/wdec/funct7
add wave -noupdate -radix hexadecimal /testbench/it/wdec/imm
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 2} {330314 ns} 0} {{Cursor 3} {330384 ns} 0}
quietly wave cursor active 2
configure wave -namecolwidth 250
configure wave -valuecolwidth 168
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {330283 ns} {330427 ns}
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