forked from Github_Repos/cvw
65 lines
1.2 KiB
Systemverilog
65 lines
1.2 KiB
Systemverilog
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//
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// File name : tb
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// Title : test
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// project : HW3
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// Library : test
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// Purpose : definition of modules for testbench
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// notes :
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//
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// Copyright Oklahoma State University
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//
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// Top level stimulus module
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`timescale 1ns/1ps
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`define XLEN 32
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module stimulus;
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logic [`XLEN-1:0] A;
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logic [$clog2(`XLEN)-1:0] Shift;
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logic [`XLEN-1:0] Z;
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logic [`XLEN-1:0] Z_corr;
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logic clk;
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integer handle3;
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integer desc3;
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integer i;
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// instatiate part to test
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shift_right dut1 (A, Shift, Z);
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assign Z_corr = (A >> Shift);
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initial
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begin
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clk = 1'b1;
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forever #5 clk = ~clk;
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end
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initial
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begin
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handle3 = $fopen("shift_right.out");
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desc3 = handle3;
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#250 $finish;
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end
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initial
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begin
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for (i=0; i < 128; i=i+1)
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begin
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// Put vectors before beginning of clk
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@(posedge clk)
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begin
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A = $random;
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Shift = $random;
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end
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@(negedge clk)
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begin
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$fdisplay(desc3, "%h %h || %h %h | %b", A, Shift, Z, Z_corr, (Z == Z_corr));
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end
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end // @(negedge clk)
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end // for (j=0; j < 32; j=j+1)
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endmodule // stimulus
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