forked from Github_Repos/cvw
77 lines
3.1 KiB
ArmAsm
77 lines
3.1 KiB
ArmAsm
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///////////////////////////////////////////
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//
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// WALLY-trap
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//
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// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
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//
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// Created 2022-02-20
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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#include "WALLY-TEST-LIB-64.h"
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INIT_TESTS
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TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
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li x28, 0x8
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csrs mstatus, x28 // set mstatus.MIE bit to 1
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// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
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// test 5.3.1.4 Basic trap tests
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// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
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CAUSE_INSTR_ACCESS
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CAUSE_ILLEGAL_INSTR
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CAUSE_BREAKPNT
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CAUSE_LOAD_ADDR_MISALIGNED
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CAUSE_LOAD_ACC
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CAUSE_STORE_ADDR_MISALIGNED
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CAUSE_STORE_ACC
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GOTO_U_MODE // Causes M mode ecall
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GOTO_S_MODE // Causes U mode ecall
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GOTO_M_MODE // Causes S mode ecall
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// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
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// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
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// CAUSE_EXT_INTERRUPT
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// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
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WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
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WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
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// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
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CAUSE_INSTR_ACCESS
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CAUSE_ILLEGAL_INSTR
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CAUSE_BREAKPNT
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CAUSE_LOAD_ADDR_MISALIGNED
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CAUSE_LOAD_ACC
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CAUSE_STORE_ADDR_MISALIGNED
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CAUSE_STORE_ACC
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CAUSE_ECALL // M mode ecall
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// GOTO_U_MODE // leave these untested since we only need to ensure that from M mode are not delegated
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// GOTO_S_MODE
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// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
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// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
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// CAUSE_EXT_INTERRUPT
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END_TESTS
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TEST_STACK_AND_DATA
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