forked from Github_Repos/cvw
74 lines
3.3 KiB
Systemverilog
74 lines
3.3 KiB
Systemverilog
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///////////////////////////////////////////
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// dtim.sv
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//
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// Written: Ross Thompson ross1728@gmail.com January 30, 2022
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// Modified:
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//
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// Purpose: simple memory with bus or cache.
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module dtim #(parameter WORDSPERLINE)
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(
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input logic clk, reset,
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input logic CPUBusy,
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input logic [1:0] LSURWM,
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input logic [`XLEN-1:0] IEUAdrM,
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input logic [`XLEN-1:0] IEUAdrE,
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input logic TrapM,
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input logic [`XLEN-1:0] FinalWriteDataM,
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output logic [`XLEN-1:0] ReadDataWordM,
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output logic BusStall,
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output logic LSUBusWrite,
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output logic LSUBusRead,
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output logic DCacheBusAck,
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output logic BusCommittedM,
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output logic [`XLEN-1:0] ReadDataWordMuxM,
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output logic DCacheStallM,
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output logic DCacheCommittedM,
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output logic DCacheWriteLine,
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output logic DCacheFetchLine,
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output logic [`PA_BITS-1:0] DCacheBusAdr,
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output logic [`XLEN-1:0] ReadDataLineSetsM [WORDSPERLINE-1:0],
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output logic DCacheMiss,
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output logic DCacheAccess);
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// *** adjust interface so write address doesn't need delaying; switch to standard RAM?
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simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
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.clk,
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.a(CPUBusy | LSURWM[0] ? IEUAdrM[31:0] : IEUAdrE[31:0]),
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.we(LSURWM[0] & ~TrapM), // have to ignore write if Trap.
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.wd(FinalWriteDataM), .rd(ReadDataWordM));
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// since we have a local memory the bus connections are all disabled.
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// There are no peripherals supported.
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assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM} = '0;
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assign ReadDataWordMuxM = ReadDataWordM;
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assign {DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0;
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assign ReadDataLineSetsM[0] = '0;
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assign {DCacheMiss, DCacheAccess} = '0;
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endmodule
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