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cvw/wally-pipelined/regression/wave-dos/peripheral-waves.do

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do script refactor
2021-04-24 13:32:09 +00:00
# peripheral-waves.do
refactored sim file
2021-03-05 19:25:16 +00:00
restart -f
delete wave /*
view wave
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 10:40:53 +00:00
# general stuff
refactored sim file
2021-03-05 19:25:16 +00:00
add wave /testbench/clk
add wave /testbench/reset
add wave -divider
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 10:40:53 +00:00
Added F_SUPPORTED flag to disable floating point unit when not in MISA
2021-07-05 14:30:46 +00:00
#add wave /testbench/dut/hart/DataStall
add wave /testbench/debug
refactored sim file
2021-03-05 19:25:16 +00:00
add wave /testbench/dut/hart/StallF
add wave /testbench/dut/hart/StallD
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 10:40:53 +00:00
add wave /testbench/dut/hart/StallE
add wave /testbench/dut/hart/StallM
add wave /testbench/dut/hart/StallW
refactored sim file
2021-03-05 19:25:16 +00:00
add wave /testbench/dut/hart/FlushD
add wave /testbench/dut/hart/FlushE
add wave /testbench/dut/hart/FlushM
add wave /testbench/dut/hart/FlushW
add wave -divider
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 10:40:53 +00:00
refactored sim file
2021-03-05 19:25:16 +00:00
add wave -hex /testbench/dut/hart/ifu/PCF
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 10:40:53 +00:00
add wave -hex /testbench/dut/hart/ifu/PCD
refactored sim file
2021-03-05 19:25:16 +00:00
add wave -hex /testbench/dut/hart/ifu/InstrD
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 14:03:19 +00:00
add wave -hex /testbench/dut/hart/ieu/c/InstrValidD
refactored sim file
2021-03-05 19:25:16 +00:00
add wave /testbench/InstrDName
add wave -divider
add wave -hex /testbench/dut/hart/ifu/PCE
add wave -hex /testbench/dut/hart/ifu/InstrE
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 14:03:19 +00:00
add wave -hex /testbench/dut/hart/ieu/c/InstrValidE
refactored sim file
2021-03-05 19:25:16 +00:00
add wave /testbench/InstrEName
add wave -hex /testbench/dut/hart/ieu/dp/SrcAE
add wave -hex /testbench/dut/hart/ieu/dp/SrcBE
add wave -hex /testbench/dut/hart/ieu/dp/ALUResultE
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 10:40:53 +00:00
#add wave /testbench/dut/hart/ieu/dp/PCSrcE
refactored sim file
2021-03-05 19:25:16 +00:00
add wave -divider
add wave -hex /testbench/dut/hart/ifu/PCM
add wave -hex /testbench/dut/hart/ifu/InstrM
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 14:03:19 +00:00
add wave -hex /testbench/dut/hart/ieu/c/InstrValidM
refactored sim file
2021-03-05 19:25:16 +00:00
add wave /testbench/InstrMName
add wave /testbench/dut/uncore/dtim/memwrite
expanded GPIO testing and caught small GPIO bug
2021-06-03 14:03:09 +00:00
add wave -hex /testbench/dut/hart/WriteDataM
swapped out linux testbench signal names
2021-07-17 18:46:18 +00:00
add wave -hex /testbench/dut/hart/lsu/dcache/MemPAdrM
add wave -hex /testbench/dut/hart/lsu/dcache/WriteDataM
add wave -hex /testbench/dut/hart/lsu/dcache/ReadDataM
expanded GPIO testing and caught small GPIO bug
2021-06-03 14:03:09 +00:00
add wave -hex /testbench/dut/hart/ebu/ReadDataM
refactored sim file
2021-03-05 19:25:16 +00:00
add wave -divider
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 10:40:53 +00:00
add wave -hex /testbench/PCW
add wave -hex /testbench/InstrW
fixed InstrValid signals and implemented less costly MEPC loading
2021-06-02 14:03:19 +00:00
add wave -hex /testbench/dut/hart/ieu/c/InstrValidW
refactored sim file
2021-03-05 19:25:16 +00:00
add wave /testbench/InstrWName
expanded GPIO testing and caught small GPIO bug
2021-06-03 14:03:09 +00:00
add wave -hex /testbench/dut/hart/ReadDataW
refactored sim file
2021-03-05 19:25:16 +00:00
add wave -hex /testbench/dut/hart/ieu/dp/ResultW
expanded GPIO testing and caught small GPIO bug
2021-06-03 14:03:09 +00:00
add wave -hex /testbench/dut/hart/ieu/dp/RegWriteW
add wave -hex /testbench/dut/hart/ieu/dp/WriteDataW
refactored sim file
2021-03-05 19:25:16 +00:00
add wave -hex /testbench/dut/hart/ieu/dp/RdW
add wave -divider
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
2021-05-29 03:11:37 +00:00
add wave -hex /testbench/dut/hart/priv/csr/TrapM
add wave -hex /testbench/dut/hart/priv/csr/UnalignedNextEPCM
add wave -hex /testbench/dut/hart/priv/csr/genblk1/csrm/WriteMEPCM
add wave -hex /testbench/dut/hart/priv/csr/genblk1/csrm/MEPC_REGW
changed stop of linux boot from arch_cpu_idle to do_idle
2021-07-16 16:27:15 +00:00
add wave -divider RegFile
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[1]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[2]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[3]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[4]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[5]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[6]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[7]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[8]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[9]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[10]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[11]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[12]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[13]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[14]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[15]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[16]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[17]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[18]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[19]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[20]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[21]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[22]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[23]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[24]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[25]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[26]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[27]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[28]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[29]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[30]
add wave -hex /testbench/dut/hart/ieu/dp/regf/rf[31]
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 10:40:53 +00:00
# peripherals
changed stop of linux boot from arch_cpu_idle to do_idle
2021-07-16 16:27:15 +00:00
add wave -divider PLIC
add wave -hex /testbench/dut/hart/priv/csr/TrapM
add wave -hex /testbench/dut/uncore/genblk2/plic/*
add wave -hex /testbench/dut/uncore/genblk2/plic/intPriority
add wave -hex /testbench/dut/uncore/genblk2/plic/pendingArray
add wave -divider UART
add wave -hex /testbench/dut/uncore/genblk4/uart/u/*
add wave -divider GPIO
add wave -hex /testbench/dut/uncore/genblk3/gpio/*
Reduced complexity of pmpadrdec
2021-06-23 07:03:52 +00:00
#add wave -divider
#add wave -hex /testbench/dut/hart/ebu/*
#add wave -divider
#add wave -divider
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 10:40:53 +00:00
# everything else
refactored sim file
2021-03-05 19:25:16 +00:00
add wave -hex -r /testbench/*
do script refactor
2021-04-24 13:32:09 +00:00
# appearance
TreeUpdate [SetDefaultTree]
WaveRestoreZoom {0 ps} {100 ps}
configure wave -namecolwidth 250
configure wave -valuecolwidth 150
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
improved PLIC test organization
2021-05-21 19:13:02 +00:00
set DefaultRadix hexadecimal
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