forked from Github_Repos/cvw
76 lines
3.1 KiB
Systemverilog
76 lines
3.1 KiB
Systemverilog
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///////////////////////////////////////////
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// 1 port sram.
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//
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// Written: ross1728@gmail.com May 3, 2021
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// Basic sram with 1 read write port.
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// When clk rises Addr and LineWriteData are sampled.
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// Following the clk edge read data is output from the sampled Addr.
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// Write
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//
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// Purpose: Storage and read/write access to data cache data, tag valid, dirty, and replacement.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words
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`include "wally-config.vh"
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module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
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input logic clk,
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input logic ce1, ce2,
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input logic [$clog2(DEPTH)-1:0] ra1,
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input logic [WIDTH-1:0] wd2,
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input logic [$clog2(DEPTH)-1:0] wa2,
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input logic we2,
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input logic [(WIDTH-1)/8:0] bwe2,
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output logic [WIDTH-1:0] rd1);
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logic [WIDTH-1:0] mem[DEPTH-1:0];
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// ***************************************************************************
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// TRUE Smem macro
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// ***************************************************************************
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// ***************************************************************************
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// READ first SRAM model
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// ***************************************************************************
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integer i;
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// Read
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always @(posedge clk)
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if(ce1) rd1 <= #1 mem[ra1];
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// Write divided into part for bytes and part for extra msbs
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if(WIDTH >= 8)
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always @(posedge clk)
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if (ce2 & we2)
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for(i = 0; i < WIDTH/8; i++)
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if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
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if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
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always @(posedge clk)
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if (ce2 & we2 & bwe2[WIDTH/8])
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mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
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endmodule
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