forked from Github_Repos/cvw
46 lines
1.9 KiB
Systemverilog
46 lines
1.9 KiB
Systemverilog
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///////////////////////////////////////////
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// csa.sv
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//
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// Written: Katherine Parry and David_Harris@hmc.edu 21 August 2022
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// Modified:
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//
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// Purpose: 3:2 carry-save adder
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module csa #(parameter N=16) (
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input logic [N-1:0] x, y, z,
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input logic cin,
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output logic [N-1:0] s, c
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);
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// This block adds x, y, z, and cin to produce
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// a result s / c in carry-save redundant form.
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// cin is just added to the least significant bit
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// s + c = x + y + z + cin
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assign s = x ^ y ^ z;
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assign c = {x[N-2:0] & (y[N-2:0] | z[N-2:0]) |
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(y[N-2:0] & z[N-2:0]), cin};
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endmodule
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