forked from Github_Repos/cvw
33 lines
691 B
Systemverilog
33 lines
691 B
Systemverilog
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module BUFGCE_DIV #(parameter string DivideAmt = "1")
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(input logic I, input logic CLR, input logic CE, output logic O);
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integer PulseCount = 0;
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logic Q;
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always_ff @(posedge I, posedge CLR) begin
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if(CLR) PulseCount <= 0;
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else begin
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if(PulseCount < (DivideAmt.atoi()/2 - 1))
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PulseCount <= PulseCount + 1;
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else
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PulseCount <= 0;
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end
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end
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assign zero = PulseCount == 0;
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flopenr #(1) ToggleFlipFLop
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(.d(~Q),
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.q(Q),
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.clk(I),
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.reset(CLR), // reset when told by outside
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.en(zero)); // only update when counter overflows
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if (DivideAmt != "1")
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assign O = Q;
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else
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assign O = I;
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endmodule
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