forked from Github_Repos/cvw
97 lines
2.6 KiB
Systemverilog
97 lines
2.6 KiB
Systemverilog
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///////////////////////////////////////////
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// SRAM2P1R1W
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//
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// Written: Ross Thomposn
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// Email: ross1728@gmail.com
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// Created: February 14, 2021
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// Modified:
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//
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// Purpose: Hacky two port SRAM model.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module SRAM2P1R1W
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#(parameter int Depth = 10,
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parameter int Width = 2
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)
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(input clk,
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// port 1 is read only
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input logic [Depth-1:0] RA1,
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output logic [Width-1:0] RD1,
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input logic REN1,
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// port 2 is write only
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input logic [Depth-1:0] WA1,
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input logic [Width-1:0] WD1,
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input logic WEN1
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);
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logic [Depth-1:0] RA1Q, WA1Q;
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logic WEN1Q;
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logic [Width-1:0] WD1Q;
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logic [2**Depth-1:0] [Width-1:0] memory;
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// SRAMs address busses are always registered first.
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flopenr #(Depth) RA1Reg(.clk(clk),
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.reset(1'b0),
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.en(REN1),
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.d(RA1),
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.q(RA1Q));
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flopenr #(Depth) WA1Reg(.clk(clk),
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.reset(1'b0),
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.en(REN1),
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.d(WA1),
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.q(WA1Q));
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flopenr #(1) WEN1Reg(.clk(clk),
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.reset(1'b0),
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.en(1'b1),
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.d(WEN1),
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.q(WEN1Q));
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flopenr #(Width) WD1Reg(.clk(clk),
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.reset(1'b0),
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.en(REN1),
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.d(WD1),
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.q(WD1Q));
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// read port
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assign RD1 = memory[RA1Q];
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// write port
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always_ff @ (posedge clk) begin
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if (WEN1Q) begin
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memory[WA1Q] = WD1Q;
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end
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end
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endmodule
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