forked from Github_Repos/cvw
72 lines
2.9 KiB
Systemverilog
72 lines
2.9 KiB
Systemverilog
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///////////////////////////////////////////
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// srt.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module srtpreproc (
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input logic [`NF:0] XManE, YManE,
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output logic [`DIVLEN-1:0] X,
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output logic [`DIVLEN-1:0] Dpreproc,
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output logic [$clog2(`NF+2)-1:0] XZeroCnt, YZeroCnt,
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output logic [$clog2(`DIVLEN/2+3)-1:0] Dur
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);
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// logic [`XLEN-1:0] PosA, PosB;
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// logic [`DIVLEN-1:0] ExtraA, ExtraB, PreprocA, PreprocB, PreprocX, PreprocY;
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logic [`DIVLEN-1:0] PreprocA, PreprocX;
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logic [`DIVLEN-1:0] PreprocB, PreprocY;
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// assign PosA = (Signed & SrcA[`XLEN - 1]) ? -SrcA : SrcA;
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// assign PosB = (Signed & SrcB[`XLEN - 1]) ? -SrcB : SrcB;
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// lzc #(`XLEN) lzcA (PosA, zeroCntA);
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// lzc #(`XLEN) lzcB (PosB, zeroCntB);
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// ***can probably merge X LZC with conversion
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// cout the number of leading zeros
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lzc #(`NF+1) lzcA (XManE, XZeroCnt);
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lzc #(`NF+1) lzcB (YManE, YZeroCnt);
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// assign ExtraA = {PosA, {`DIVLEN-`XLEN{1'b0}}};
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// assign ExtraB = {PosB, {`DIVLEN-`XLEN{1'b0}}};
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// assign PreprocA = ExtraA << zeroCntA;
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// assign PreprocB = ExtraB << (zeroCntB + 1);
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assign PreprocX = {XManE[`NF-1:0]<<XZeroCnt, {`DIVLEN-`NF{1'b0}}};
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assign PreprocY = {YManE[`NF-1:0]<<YZeroCnt, {`DIVLEN-`NF{1'b0}}};
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assign X = PreprocX;
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assign Dpreproc = PreprocY;
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assign Dur = ($clog2(`DIVLEN/2+3))'(`DIVLEN/2+2);
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// assign intExp = zeroCntB - zeroCntA + 1;
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// assign intSign = Signed & (SrcA[`XLEN - 1] ^ SrcB[`XLEN - 1]);
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endmodule
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