forked from Github_Repos/cvw
85 lines
3.2 KiB
Systemverilog
85 lines
3.2 KiB
Systemverilog
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///////////////////////////////////////////
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// srt.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, Cedar Turek
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// Modified:13 January 2022
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//
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// Purpose: Combined Divide and Square Root Floating Point and Integer Unit
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module srtfsm(
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input logic clk,
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input logic reset,
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input logic [`DIVLEN+3:0] WSN, WCN, WS, WC,
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input logic XInfE, YInfE,
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input logic XZeroE, YZeroE,
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input logic XNaNE, YNaNE,
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input logic DivStart,
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input logic StallE,
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input logic StallM,
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input logic [$clog2(`DIVLEN/2+3)-1:0] Dur,
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output logic [$clog2(`DIVLEN/2+3)-1:0] EarlyTermShiftDiv2E,
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output logic DivStickyE,
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output logic DivDone,
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output logic DivNegStickyE,
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output logic DivBusy
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);
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typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype;
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statetype state;
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logic [$clog2(`DIVLEN/2+3)-1:0] step;
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logic WZero;
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//logic [$clog2(`DIVLEN/2+3)-1:0] Dur;
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logic [`DIVLEN+3:0] W;
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//flopen #($clog2(`DIVLEN/2+3)) durflop(clk, DivStart, CalcDur, Dur);
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assign DivBusy = (state == BUSY);
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assign WZero = ((WSN^WCN)=={WSN[`DIVLEN+2:0]|WCN[`DIVLEN+2:0], 1'b0});
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assign DivStickyE = ~WZero;
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assign DivDone = (state == DONE);
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assign W = WC+WS;
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assign DivNegStickyE = W[`DIVLEN+3]; //*** is there a better way to do this???
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assign EarlyTermShiftDiv2E = step;
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always_ff @(posedge clk) begin
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if (reset) begin
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state <= #1 IDLE;
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end else if (DivStart&~StallE) begin
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step <= Dur;
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if (XZeroE|YZeroE|XInfE|YInfE|XNaNE|YNaNE) state <= #1 DONE;
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else state <= #1 BUSY;
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end else if (state == BUSY) begin
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if ((~|step[$clog2(`DIVLEN/2+3)-1:1]&step[0])|WZero) begin
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state <= #1 DONE;
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end
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step <= step - 1;
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end else if (state == DONE) begin
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if (StallM) state <= #1 DONE;
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else state <= #1 IDLE;
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end
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end
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endmodule
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