forked from Github_Repos/cvw
57 lines
2.3 KiB
Systemverilog
57 lines
2.3 KiB
Systemverilog
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///////////////////////////////////////////
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//
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// Written: Katherine Parry
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// Modified: 6/23/2021
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//
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// Purpose: FPU Sign Injection instructions
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fsgninj (
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input logic XSgnE, YSgnE, // X and Y sign bits
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input logic [63:0] FSrcXE, // X
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input logic FmtE, // precision 1 = double 0 = single
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input logic [1:0] SgnOpCodeE, // operation control
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output logic [63:0] SgnResE // result
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);
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logic ResSgn;
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//op code designation:
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//
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//00 - fsgnj - directly copy over sign value of FSrcYE
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//01 - fsgnjn - negate sign value of FSrcYE
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//10 - fsgnjx - XOR sign values of FSrcXE & FSrcYE
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//
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// calculate the result's sign
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assign ResSgn = SgnOpCodeE[1] ? (XSgnE ^ YSgnE) : (YSgnE ^ SgnOpCodeE[0]);
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// format final result based on precision
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// - uses NaN-blocking format
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// - if there are any unsused bits the most significant bits are filled with 1s
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assign SgnResE = FmtE ? {ResSgn, FSrcXE[62:0]} : {FSrcXE[63:32], ResSgn, FSrcXE[30:0]};
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endmodule
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