forked from Github_Repos/cvw
54 lines
1.4 KiB
Systemverilog
54 lines
1.4 KiB
Systemverilog
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module testbench();
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logic clk, reset;
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// DUT inputs
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logic [31:0] PCF;
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logic [31:0] PageTableEntryF;
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logic ITLBWriteF, ITLBFlushF;
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// DUT outputs
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logic [31:0] PCPF;
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logic ITLBMissF, ITLBHitF;
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// Testbench signals
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logic [33:0] expected;
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logic [31:0] vectornum, errors;
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logic [99:0] testvectors[10000:0];
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// instantiate device under test
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tlb_toy dut(.*);
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// generate clock
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always begin
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clk=1; #5; clk=0; #5;
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end
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// at start of test, load vectors and pulse reset
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initial begin
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$readmemb("tlb_toy.tv", testvectors);
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vectornum = 0; errors = 0; reset = 1; #22; reset = 0;
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end
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// apply test vectors on rising edge of clk
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always @(posedge clk) begin
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#1; {PCF, PageTableEntryF, ITLBWriteF, ITLBFlushF, expected} = testvectors[vectornum];
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end
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// check results on falling edge of clk
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always @(negedge clk)
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if (~reset) begin // skip during reset
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if ({PCPF, ITLBMissF, ITLBHitF} !== expected) begin // check result
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$display("Error: PCF = %b, write = %b, data = %b, flush = %b", PCF,
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ITLBWriteF, PageTableEntryF, ITLBFlushF);
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$display(" outputs = %b %b %b (%b expected)",
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PCPF, ITLBMissF, ITLBHitF, expected);
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errors = errors + 1;
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end
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vectornum = vectornum + 1;
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if (testvectors[vectornum] === 100'bx) begin
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$display("%d tests completed with %d errors", vectornum, errors);
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$stop;
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end
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end
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endmodule
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