forked from Github_Repos/cvw
85 lines
3.4 KiB
Systemverilog
85 lines
3.4 KiB
Systemverilog
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///////////////////////////////////////////
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// uart.sv
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//
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// Written: David_Harris@hmc.edu 21 January 2021
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// Modified:
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//
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// Purpose: Interface to Universial Asynchronous Receiver/ Transmitter with FIFOs
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// Emulates interface of Texas Instruments PC165550D
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// Compatible with UART in Imperas Virtio model ***
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-macros.sv"
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module uart #(parameter XLEN=32) (
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input logic clk, reset,
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input logic [1:0] MemRWgpioM,
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input logic [7:0] ByteMaskM,
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input logic [XLEN-1:0] AdrM,
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input logic [XLEN-1:0] MaskedWriteDataM,
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output logic [XLEN-1:0] RdUARTM,
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input logic SIN, DSRb, DCDb, CTSb, RIb, // from E1A driver from RS232 interface
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output logic SOUT, RTSb, DTRb, // to E1A driver to RS232 interface
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output logic OUT1b, OUT2b, INTR, TXRDYb, RXRDYb); // to CPU
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// UART interface signals
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logic [2:0] A;
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logic MEMRb, MEMWb;
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logic [7:0] Din, Dout;
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logic SINint; // for loopback testing
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// rename processor interface signals to match PC16550D and provide one-byte interface
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assign MEMRb = ~MemRWgpioM[1];
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assign MEMWb = ~MemRWgpioM[0];
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assign A = AdrM[2:0];
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generate
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if (XLEN == 64) begin
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always_comb begin
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/* RdUARTM = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
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case (AdrM[2:0])
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3'b000: Din = MaskedWriteDataM[7:0];
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3'b001: Din = MaskedWriteDataM[15:8];
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3'b010: Din = MaskedWriteDataM[23:16];
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3'b011: Din = MaskedWriteDataM[31:24];
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3'b100: Din = MaskedWriteDataM[39:32];
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3'b101: Din = MaskedWriteDataM[47:40];
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3'b110: Din = MaskedWriteDataM[55:48];
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3'b111: Din = MaskedWriteDataM[63:56];
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endcase */
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end
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end else begin // 32-bit
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always_comb begin
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RdUARTM = {Dout, Dout, Dout, Dout};
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case (AdrM[1:0])
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2'b00: Din = MaskedWriteDataM[7:0];
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2'b01: Din = MaskedWriteDataM[15:8];
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2'b10: Din = MaskedWriteDataM[23:16];
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2'b11: Din = MaskedWriteDataM[31:24];
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endcase
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end
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end
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endgenerate
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logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK
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uartPC16550D u(.RCLK(BAUDOUTb), .*);
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endmodule
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