forked from Github_Repos/cvw
53 lines
2.0 KiB
Systemverilog
53 lines
2.0 KiB
Systemverilog
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///////////////////////////////////////////
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// mux.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Various flavors of multiplexers
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-macros.sv"
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module mux2 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1,
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input logic s,
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output logic [WIDTH-1:0] y);
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assign y = s ? d1 : d0;
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endmodule
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module mux3 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1, d2,
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input logic [1:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[1] ? d2 : (s[0] ? d1 : d0);
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endmodule
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module mux4 #(parameter WIDTH = 8) (
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input logic [WIDTH-1:0] d0, d1, d2, d3,
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input logic [1:0] s,
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output logic [WIDTH-1:0] y);
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assign y = s[1] ? (s[0] ? d3 : d2) : (s[0] ? d1 : d0);
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endmodule
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