forked from Github_Repos/cvw
60 lines
2.2 KiB
Systemverilog
60 lines
2.2 KiB
Systemverilog
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///////////////////////////////////////////
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// bigendianswap.sv
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//
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// Written: David_Harris@hmc.edu 7 May 2022
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// Modified:
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//
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// Purpose: Swap byte order for Big-Endian accesses
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module bigendianswap (
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input logic BigEndianM,
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input logic [`XLEN-1:0] a,
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output logic [`XLEN-1:0] y);
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if(`XLEN == 64) begin
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always_comb
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if (BigEndianM) begin // swap endianness
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y[63:56] = a[7:0];
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y[55:48] = a[15:8];
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y[47:40] = a[23:16];
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y[39:32] = a[31:24];
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y[31:24] = a[39:32];
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y[23:16] = a[47:40];
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y[15:8] = a[55:48];
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y[7:0] = a[63:56];
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end else y = a;
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end else begin
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always_comb
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if (BigEndianM) begin
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y[31:24] = a[7:0];
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y[23:16] = a[15:8];
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y[15:8] = a[23:16];
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y[7:0] = a[31:24];
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end else y = a;
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end
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endmodule
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