cvw/fpga/constraints
2023-07-24 10:47:05 -05:00
..
artyddr3.ucf
constraints-ArtyA7.xdc Merge branch 'main' of github.com:ross144/cvw 2023-07-24 10:47:05 -05:00
constraints-vcu108.xdc
constraints-vcu118.xdc
debug2.xdc Merge branch 'boot' into mergeBoot 2023-07-21 17:43:45 -05:00
debug4.xdc I think the fpga is building again, but the debugger script needs to be updated. For some reason the nets are not present despite being marked debug. 2023-06-16 17:00:27 -05:00
marked_debug.txt Merge branch 'boot' into mergeBoot 2023-07-21 17:43:45 -05:00
small-debug.xdc Fixed a bunch of timing constraints for the arty a7 board. 2023-07-19 17:08:16 -05:00
test.file
vcu-small-debug.xdc Working new boot process. Buildroot package for sdc. 2023-07-20 14:15:59 -05:00