cvw/pipelined/src
2022-11-06 23:32:38 +00:00
..
cache comment updates. 2022-10-22 16:28:44 -05:00
ebu Merged cacheable with seluncachedadr. 2022-10-17 13:29:21 -05:00
fpu propagated otfc swap to Rad2 and 4 qslc 2022-11-06 23:32:38 +00:00
generic
hazard Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline. 2022-10-22 16:27:20 -05:00
ieu
ifu Moving interlockfsm changes to a temporary branch. 2022-10-19 15:08:23 -05:00
lsu Found a way to remove the interlock fsm. Dramatically reducing the complexity of virtual memory and page table walks. 2022-10-23 13:46:50 -05:00
mmu HPTW cleanup 2022-11-04 15:21:09 -07:00
muldiv
ppa
privileged Moving interlockfsm changes to a temporary branch. 2022-10-19 15:08:23 -05:00
uncore Fixed the uart transmit fifo overrun bug. 2022-10-26 14:48:09 -05:00
wally
sdc