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Changed FDivBusyE to stall the whole pipeline. Any instruction in the Executation which depended on the output of an instruction in the writeback stage would be lost if the back end of the pipelined advanced. The solution is to stall the whole pipeline.

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Ross Thompson 2022-10-22 16:27:20 -05:00
parent a45e612008
commit 611ea6882d
1 changed files with 2 additions and 2 deletions
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pipelined/src/hazard/hazard.sv
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@ -69,8 +69,8 @@ module hazard(
assign StallECause = (DivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?)
// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
// assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE;
assign StallMCause = ((wfiM | FDivBusyE) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE?
assign StallWCause = LSUStallM | IFUStallF;
assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE?
assign StallWCause = LSUStallM | IFUStallF | (FDivBusyE & ~TrapM & ~IntPendingM);
assign #1 StallF = StallFCause | StallD;
assign #1 StallD = StallDCause | StallE;