mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 13:04:28 +00:00
83 lines
3.2 KiB
XML
83 lines
3.2 KiB
XML
FROM wallysoc/ubuntu_wally
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# SET ENVIRONMENT VARIABLES
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# assume 4 threads are available to speed up
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ARG NUM_THREADS=4
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ENV RISCV=/opt/riscv
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WORKDIR /opt/riscv
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# TOOLCHAIN
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RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
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cd riscv-gnu-toolchain && \
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sed -i 's/https/git/' .gitmodules && git submodule sync && \
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./configure --prefix=${RISCV} --enable-multilib \
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--with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
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make --jobs ${NUM_THREADS} && \
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make install && cd ${RISCV} && \
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rm -rf ${RISCV}/riscv-gnu-toolchain
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# # TOOLCHAIN
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# RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
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# cd riscv-gnu-toolchain && \
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# sed -i 's/https/git/' .gitmodules && git submodule sync && \
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# ./configure --prefix=${RISCV} --enable-multilib \
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# --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"
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# RUN cd riscv-gnu-toolchain && make --jobs ${NUM_THREADS}
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# RUN cd riscv-gnu-toolchain && make install && cd ${RISCV}
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# RUN cd riscv-gnu-toolchain && rm -rf ${RISCV}/riscv-gnu-toolchain
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# elf2hex
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RUN git clone https://github.com/sifive/elf2hex.git && \
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cd elf2hex && \
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autoreconf -i && \
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./configure --target=riscv64-unknown-elf --prefix=${RISCV} && \
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make && \
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make install && cd ${RISCV} && \
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rm -rf ${RISCV}/elf2hex
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# QEMU
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RUN git clone --recursive https://github.com/qemu/qemu && \
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cd qemu && \
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./configure --target-list=riscv64-softmmu --prefix=${RISCV} && \
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make --jobs ${NUM_THREADS} && \
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make install && cd ${RISCV} && \
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rm -rf ${RISCV}/qemu
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# Spike
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RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
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mkdir riscv-isa-sim/build && \
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cd riscv-isa-sim/build && \
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../configure --prefix=$RISCV --enable-commitlog && \
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make --jobs ${NUM_THREADS} && \
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make install && cd ${RISCV} && \
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rm -rf ${RISCV}/riscv-isa-sim
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# SAIL
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RUN opam init -y --disable-sandboxing && \
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opam switch create 5.1.0 && \
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opam install sail -y && \
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eval $(opam config env) && \
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git clone https://github.com/riscv/sail-riscv.git && \
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cd sail-riscv && \
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ARCH=RV32 make c_emulator/riscv_sim_RV32 && \
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ARCH=RV64 make c_emulator/riscv_sim_RV64 && \
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ln -s ${RISCV}/sail-riscv/c_emulator/riscv_sim_RV64 ${RISCV}/bin/riscv_sim_RV64 && \
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ln -s ${RISCV}/sail-riscv/c_emulator/riscv_sim_RV32 ${RISCV}/bin/riscv_sim_RV32 && \
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rm -rf ${RISCV}/sail-riscv
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# Buildroot
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RUN git clone https://github.com/buildroot/buildroot.git && \
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cd buildroot && \
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git checkout 2021.05 && \
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# cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
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# cp ./board/wally/main.config .config && \
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wget https://raw.githubusercontent.com/openhwgroup/cvw/main/linux/buildroot-config-src/wally/main.config -o .config && \
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make --jobs ${NUM_THREADS}
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RUN pip3 install --no-cache-dir \
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testresources riscv_config \
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git+https://github.com/riscv/riscof.git
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USER ${USERNAME} |