FROM wallysoc/ubuntu_wally

# SET ENVIRONMENT VARIABLES
# assume 4 threads are available to speed up
ARG NUM_THREADS=4
ENV RISCV=/opt/riscv

WORKDIR /opt/riscv

# TOOLCHAIN
RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
    cd riscv-gnu-toolchain && \
    sed -i 's/https/git/' .gitmodules && git submodule sync && \
    ./configure --prefix=${RISCV} --enable-multilib \
        --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
    make --jobs ${NUM_THREADS} && \
    make install && cd ${RISCV} && \
    rm -rf ${RISCV}/riscv-gnu-toolchain

# # TOOLCHAIN
# RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
#     cd riscv-gnu-toolchain && \
#     sed -i 's/https/git/' .gitmodules && git submodule sync && \
#     ./configure --prefix=${RISCV} --enable-multilib \
#         --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;"

# RUN cd riscv-gnu-toolchain && make --jobs ${NUM_THREADS}
# RUN cd riscv-gnu-toolchain && make install && cd ${RISCV}
# RUN cd riscv-gnu-toolchain && rm -rf ${RISCV}/riscv-gnu-toolchain

# elf2hex
RUN git clone https://github.com/sifive/elf2hex.git && \
    cd elf2hex && \
    autoreconf -i && \
    ./configure --target=riscv64-unknown-elf --prefix=${RISCV} && \
    make && \
    make install && cd ${RISCV} && \
    rm -rf ${RISCV}/elf2hex

# QEMU
RUN git clone --recursive https://github.com/qemu/qemu && \
    cd qemu && \
    ./configure --target-list=riscv64-softmmu --prefix=${RISCV}  && \
    make --jobs ${NUM_THREADS} && \
    make install && cd ${RISCV} && \
    rm -rf ${RISCV}/qemu

# Spike
RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
    mkdir riscv-isa-sim/build && \
    cd riscv-isa-sim/build && \
    ../configure --prefix=$RISCV --enable-commitlog && \
    make --jobs ${NUM_THREADS} && \
    make install && cd ${RISCV} && \
    rm -rf ${RISCV}/riscv-isa-sim

# SAIL
RUN opam init -y --disable-sandboxing && \
    opam switch create 5.1.0 && \
    opam install sail -y && \
    eval $(opam config env) && \
    git clone https://github.com/riscv/sail-riscv.git && \
    cd sail-riscv && \
    ARCH=RV32 make c_emulator/riscv_sim_RV32 && \
    ARCH=RV64 make c_emulator/riscv_sim_RV64 && \
    ln -s ${RISCV}/sail-riscv/c_emulator/riscv_sim_RV64 ${RISCV}/bin/riscv_sim_RV64 && \
    ln -s ${RISCV}/sail-riscv/c_emulator/riscv_sim_RV32 ${RISCV}/bin/riscv_sim_RV32 && \
    rm -rf ${RISCV}/sail-riscv

# Buildroot
RUN git clone https://github.com/buildroot/buildroot.git && \
    cd buildroot && \
    git checkout 2021.05 && \
    # cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
    # cp ./board/wally/main.config .config && \
    wget https://raw.githubusercontent.com/openhwgroup/cvw/main/linux/buildroot-config-src/wally/main.config -o .config && \
    make --jobs ${NUM_THREADS}

RUN pip3 install --no-cache-dir \
    testresources riscv_config \
    git+https://github.com/riscv/riscof.git

USER ${USERNAME}