Rose Thompson 26cd22c388 Replaced fpga's verilog top with system verilog.		2023-12-15 13:42:52 -06:00
..
artyddr3.ucf
constraints-ArtyA7.xdc
constraints-vcu108.xdc
constraints-vcu118.xdc
debug2.xdc
debug4.xdc
marked_debug_all.txt
marked_debug_small.txt
marked_debug.txt	Get's the fpga building again after the git history rewrite.	2023-12-14 17:08:25 -06:00
small-debug.xdc	Replaced fpga's verilog top with system verilog.	2023-12-15 13:42:52 -06:00
vcu-small-debug.xdc