Rose Thompson 6a4c8667df Added new signals to ILA to debug the RVVI tracer. ... The tracer appears to be stuck and the CPU is never getting out of (into reset).		2024-05-30 16:43:25 -05:00
..
artyddr3.ucf
constraints-ArtyA7.xdc	The FPGA is synthesizing with the rvvi and ethernet hardware.	2024-05-30 15:37:17 -05:00
constraints-vcu108.xdc
constraints-vcu118.xdc	Pushed vcu118 to 71MHz.	2023-08-25 17:04:50 -05:00
debug2.xdc
debug4.xdc	Added help option to the flash-sd script.	2023-08-22 13:37:33 -05:00
marked_debug_all.txt
marked_debug_small.txt
marked_debug.txt	Get's the fpga building again after the git history rewrite.	2023-12-14 17:08:25 -06:00
small-debug.xdc	Added new signals to ILA to debug the RVVI tracer.	2024-05-30 16:43:25 -05:00
vcu-small-debug.xdc