Rose Thompson 6a4c8667df Added new signals to ILA to debug the RVVI tracer. ... The tracer appears to be stuck and the CPU is never getting out of (into reset).		2024-05-30 16:43:25 -05:00
..
artyddr3.ucf	Added more support for Arty A7 board.	2023-04-10 16:01:17 -05:00
constraints-ArtyA7.xdc	The FPGA is synthesizing with the rvvi and ethernet hardware.	2024-05-30 15:37:17 -05:00
constraints-vcu108.xdc	Added sdio_cd to vcu108 constraints. Removed SDC signals from uncore	2023-03-24 17:01:27 -05:00
constraints-vcu118.xdc	Pushed vcu118 to 71MHz.	2023-08-25 17:04:50 -05:00
debug2.xdc	Merge branch 'boot' into mergeBoot	2023-07-21 17:43:45 -05:00
debug4.xdc	Added help option to the flash-sd script.	2023-08-22 13:37:33 -05:00
marked_debug_all.txt	Updated artyA7 debugger to match book.	2023-08-21 14:35:42 -05:00
marked_debug_small.txt	Updated artyA7 debugger to match book.	2023-08-21 14:35:42 -05:00
marked_debug.txt	Get's the fpga building again after the git history rewrite.	2023-12-14 17:08:25 -06:00
small-debug.xdc	Added new signals to ILA to debug the RVVI tracer.	2024-05-30 16:43:25 -05:00
vcu-small-debug.xdc	Working new boot process. Buildroot package for sdc.	2023-07-20 14:15:59 -05:00