Rose Thompson 7358c1fe67 Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status.		2024-11-25 15:50:29 -06:00
..
bios.S	Revert "Revmoed file from fpga zbbl which should not have been added."	2024-10-14 21:29:02 -05:00
boot.c	Reverted bootloader optimizations to second iteration. Working on last optimization.	2024-11-02 14:14:31 -05:00
boot.h	Added MAXSDCCLOCK to parameters set by the FPGA makefile.	2024-09-03 10:55:15 -07:00
fail.c
fail.h
gpt.c
gpt.h
linker1000.x	Update linker scripts to avoid hardcoded /opt/riscv	2024-08-09 20:15:28 -07:00
Makefile	Update all iterative makes to use	2024-09-29 23:14:19 -07:00
riscv.h
riscv.S
sd.c
sd.h
spi.c	Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status.	2024-11-25 15:50:29 -06:00
spi.h	Fixed sublte bug in the spi_fifo which allows for spurious write to fifo. Fixed fpga zsbl so that is uses read fifo interrupt pending (IP) rather than transmit fifo IP. Resolves issue with stalled load reading the wrong fifo status.	2024-11-25 15:50:29 -06:00
splitfile.sh	Added and extra header and changed the comments to be accurate in ram1p1rwbe.sv	2024-08-06 17:36:42 -05:00
system.h	Added MAXSDCCLOCK to parameters set by the FPGA makefile.	2024-09-03 10:55:15 -07:00
time.c
time.h
uart.c
uart.h