David Harris f03d4e6b5a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main		2022-12-20 14:43:33 -08:00
..
cache	Renamed renamed sram to ram	2022-12-20 08:36:45 -08:00
ebu	Rough draft of cache flush fsm enhancement.	2022-12-16 15:28:22 -06:00
fpu	FPU remove unused signals	2022-12-20 14:43:30 -08:00
generic	Memory cleanup	2022-12-20 11:22:26 -08:00
hazard	Explained hazard causes	2022-12-19 09:41:41 -08:00
ieu	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
ifu	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-12-20 14:43:33 -08:00
lsu	Renamed renamed sram to ram	2022-12-20 08:36:45 -08:00
mmu	Moved CPUBusy out of HPTW.	2022-12-11 15:48:00 -06:00
muldiv	Use FlushE to reset integer divider FSM	2022-12-15 11:00:54 -08:00
ppa	cleanup, plots for paper	2022-06-15 18:28:36 +00:00
privileged	Replaced || and && with single ops	2022-12-20 01:33:35 -08:00
uncore	FPU remove unused signals	2022-12-20 14:43:30 -08:00
wally	Renamed FStallD to FPUStallD.	2022-12-19 09:28:45 -06:00
sdc	piplined directory cleanup	2022-01-07 12:43:50 +00:00