cvw/fpga/generator
2024-10-01 12:19:12 -07:00
..
debug
ahbaxibridge.tcl More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00
clkconverter.tcl More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00
ddr3-ArtyA7.tcl More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00
ddr4-vcu108.tcl This actually fixes the vcu108 to correctly set the SPI clock frequency. 2024-09-03 13:11:03 -07:00
ddr4-vcu118.tcl Fixed bugs in the fpga Makefile and vcu118 ddr memory gen script. 2024-09-03 21:03:38 -07:00
insert_debug_comment.sh
Makefile Fixed bugs in the fpga Makefile and vcu118 ddr memory gen script. 2024-09-03 21:03:38 -07:00
mmcm.tcl Finally worked out that subtle bug in the tcl scripts clock setting. 2024-09-03 10:30:34 -07:00
probe
sysrst.tcl More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00
wally.tcl Added spi debugger to build script. 2024-09-05 12:04:14 -07:00
wave_config.wcfg remove hard-code path in wave_config.wcfg even though its probably not needed. Its a generated file. I believe the path doesn't matter, so I removed it. 2024-09-18 15:40:00 -05:00
xlnx_ddr3-artya7-mig.prj
xlnx_ddr4.tcl More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00