mirror of
https://github.com/openhwgroup/cvw
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106 lines
3.5 KiB
ArmAsm
106 lines
3.5 KiB
ArmAsm
///////////////////////////////////////////
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// ifu.S
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//
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// Written: sriley@g.hmc.edu 28 March 2023
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//
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// Purpose: Test coverage for IFU
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// load code to initalize stack, handle interrupts, terminate
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#include "WALLY-init-lib.h"
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main:
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# turn floating point on
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li t0, 0x2000
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csrs mstatus, t0
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# calling compressed floating point load double instruction
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//.hword 0x2000 // CL type compressed floating-point ld-->funct3,imm,rs1',imm,rd',op
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// binary version 0000 0000 0000 0000 0010 0000 0000 0000
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mv s0, sp
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c.fld fs0, 0(s0) // Previously uncovered instructions
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c.fsd fs0, 0(s0)
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.hword 0x2002 // c.fldsp fs0, 0
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.hword 0xA002 // c.fsdsp fs0, 0
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.hword 0x9C41 // line 134 Illegal compressed instruction
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# Zcb coverage tests
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# could restore assembly language versions when GCC supports Zcb
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mv s0, sp
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#c.lbu s1, 0(s0) // exercise c.lbu
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.hword 0x8004 // c.lbu s1, 0(s0)
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#c.lh s1, 0(s0) // exercise c.lh
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.hword 0x8444 // c.lh s1, 0(s0)
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#c.lhu s1, 0(s0) // exercise c.lhu
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.hword 0x8404 // c.lhu s1, 0(s0)
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#c.sb s1, 0(s0) // exercise c.sb
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.hword 0x8804 // c.sb s1, 0(s0)
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#c.sh s1, 0(s0) // exercise c.sh
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.hword 0x8C04 // c.sh s1, 0(s0)
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.hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction
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.hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction
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li s0, 0xFF
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# c.zext.b s0 // exercise c.zext.b
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.hword 0x9C61 // c.zext.b s0
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# c.sext.b s0 // exercise c.sext.b
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.hword 0x9C65 // c.sext.b s0
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# c.zext.h s0 // exercise c.zext.h
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.hword 0x9C69 // c.zext.h s0
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# c.sext.h s0 // exercise c.sext.h
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.hword 0x9C6D // c.sext.h s0
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# c.zext.w s0 // exercise c.zext.w
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.hword 0x9C71 // c.zext.w s0
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# c.not s0 // exercise c.not
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.hword 0x9C75 // c.not s0
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.hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else
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# exercise all the cache ways
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j way0code
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# stress test cache ways by loading stuff from each one and then doing fence.i to invalidate
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.align 12
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way0code:
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jal way1code
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fence.i
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j done
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.align 12
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way1code:
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j way2code
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.align 12
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way2code:
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j way3code
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.align 12
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way3code:
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j way00code
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.align 12
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way00code:
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ret
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j done
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