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59 lines
2.8 KiB
Systemverilog
59 lines
2.8 KiB
Systemverilog
///////////////////////////////////////////
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// tlblru.sv
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//
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// Written: tfleming@hmc.edu & jtorrey@hmc.edu 16 February 2021
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// Modified:
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//
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// Purpose: Implementation of bit pseudo least-recently-used algorithm for
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// cache evictions. Outputs the index of the next entry to be written.
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module tlblru #(parameter TLB_ENTRIES = 8) (
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input logic clk, reset,
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input logic TLBWrite,
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input logic TLBFlush,
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input logic [TLB_ENTRIES-1:0] Matches,
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input logic CAMHit,
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output logic [TLB_ENTRIES-1:0] WriteEnables
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);
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logic [TLB_ENTRIES-1:0] RUBits, RUBitsNext, RUBitsAccessed;
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logic [TLB_ENTRIES-1:0] WriteLines;
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logic [TLB_ENTRIES-1:0] AccessLines; // One-hot encodings of which line is being accessed
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logic AllUsed; // High if the next access causes all RU bits to be 1
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// Find the first line not recently used
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priorityonehot #(TLB_ENTRIES) nru(.a(~RUBits), .y(WriteLines));
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// Track recently used lines, updating on a CAM Hit or TLB write
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assign WriteEnables = WriteLines & {(TLB_ENTRIES){TLBWrite}};
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assign AccessLines = TLBWrite ? WriteLines : Matches;
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assign RUBitsAccessed = AccessLines | RUBits;
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assign AllUsed = &RUBitsAccessed; // if all recently used, then clear to none
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assign RUBitsNext = AllUsed ? 0 : RUBitsAccessed;
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// enable must be ORd with TLBFlush to ensure flop fires on a flush. DH 7/8/21
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flopenrc #(TLB_ENTRIES) lrustate(clk, reset, TLBFlush, (CAMHit | TLBWrite), RUBitsNext, RUBits);
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endmodule
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